1 /*
2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
7  *
8  * Based on SPL code from Solidrun tree, which is:
9  * Author: Tungyi Lin <tungyilin1127@gmail.com>
10  *
11  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
12  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
13  *
14  * SPDX-License-Identifier:	GPL-2.0+
15  */
16 
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/iomux.h>
20 #include <asm/arch/mx6-pins.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/errno.h>
23 #include <asm/gpio.h>
24 #include <asm/imx-common/iomux-v3.h>
25 #include <asm/imx-common/video.h>
26 #include <mmc.h>
27 #include <fsl_esdhc.h>
28 #include <malloc.h>
29 #include <miiphy.h>
30 #include <netdev.h>
31 #include <asm/arch/crm_regs.h>
32 #include <asm/io.h>
33 #include <asm/arch/sys_proto.h>
34 #include <spl.h>
35 #include <usb.h>
36 #include <usb/ehci-fsl.h>
37 
38 DECLARE_GLOBAL_DATA_PTR;
39 
40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
41 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
42 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
43 
44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
45 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
46 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
47 
48 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
49 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
50 
51 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |		\
52 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
53 
54 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
55 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
56 
57 #define ETH_PHY_RESET	IMX_GPIO_NR(4, 15)
58 #define USB_H1_VBUS	IMX_GPIO_NR(1, 0)
59 
60 int dram_init(void)
61 {
62 	gd->ram_size = imx_ddr_size();
63 	return 0;
64 }
65 
66 static iomux_v3_cfg_t const uart1_pads[] = {
67 	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
68 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
69 };
70 
71 static iomux_v3_cfg_t const usdhc2_pads[] = {
72 	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73 	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 };
79 
80 static iomux_v3_cfg_t const hb_cbi_sense[] = {
81 	/* These pins are for sensing if it is a CuBox-i or a HummingBoard */
82 	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
83 	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
84 };
85 
86 static iomux_v3_cfg_t const usb_pads[] = {
87 	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 };
89 
90 static void setup_iomux_uart(void)
91 {
92 	SETUP_IOMUX_PADS(uart1_pads);
93 }
94 
95 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
96 	{USDHC2_BASE_ADDR},
97 };
98 
99 int board_mmc_getcd(struct mmc *mmc)
100 {
101 	return 1; /* uSDHC2 is always present */
102 }
103 
104 int board_mmc_init(bd_t *bis)
105 {
106 	SETUP_IOMUX_PADS(usdhc2_pads);
107 	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
108 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
109 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
110 
111 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
112 }
113 
114 static iomux_v3_cfg_t const enet_pads[] = {
115 	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
116 	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
117 	/* AR8035 reset */
118 	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
119 	/* AR8035 interrupt */
120 	IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
121 	/* GPIO16 -> AR8035 25MHz */
122 	IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK	  | MUX_PAD_CTRL(NO_PAD_CTRL)),
123 	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC	  | MUX_PAD_CTRL(NO_PAD_CTRL)),
124 	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
125 	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
126 	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
127 	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
128 	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
129 	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
130 	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
131 	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
132 	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
133 	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
134 	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
135 	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
136 	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
137 	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
138 	IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
139 };
140 
141 static void setup_iomux_enet(void)
142 {
143 	SETUP_IOMUX_PADS(enet_pads);
144 
145 	gpio_direction_output(ETH_PHY_RESET, 0);
146 	mdelay(10);
147 	gpio_set_value(ETH_PHY_RESET, 1);
148 	udelay(100);
149 }
150 
151 int board_phy_config(struct phy_device *phydev)
152 {
153 	if (phydev->drv->config)
154 		phydev->drv->config(phydev);
155 
156 	return 0;
157 }
158 
159 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
160 #define ETH_PHY_MASK	((1 << 0x0) | (1 << 0x4))
161 
162 int board_eth_init(bd_t *bis)
163 {
164 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
165 	struct mii_dev *bus;
166 	struct phy_device *phydev;
167 
168 	int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
169 	if (ret)
170 		return ret;
171 
172 	/* set gpr1[ENET_CLK_SEL] */
173 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
174 
175 	setup_iomux_enet();
176 
177 	bus = fec_get_miibus(IMX_FEC_BASE, -1);
178 	if (!bus)
179 		return -EINVAL;
180 
181 	phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
182 	if (!phydev) {
183 		ret = -EINVAL;
184 		goto free_bus;
185 	}
186 
187 	debug("using phy at address %d\n", phydev->addr);
188 	ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
189 	if (ret)
190 		goto free_phydev;
191 
192 	return 0;
193 
194 free_phydev:
195 	free(phydev);
196 free_bus:
197 	free(bus);
198 	return ret;
199 }
200 
201 #ifdef CONFIG_VIDEO_IPUV3
202 static void do_enable_hdmi(struct display_info_t const *dev)
203 {
204 	imx_enable_hdmi_phy();
205 }
206 
207 struct display_info_t const displays[] = {
208 	{
209 		.bus	= -1,
210 		.addr	= 0,
211 		.pixfmt	= IPU_PIX_FMT_RGB24,
212 		.detect	= detect_hdmi,
213 		.enable	= do_enable_hdmi,
214 		.mode	= {
215 			.name           = "HDMI",
216 			/* 1024x768@60Hz (VESA)*/
217 			.refresh        = 60,
218 			.xres           = 1024,
219 			.yres           = 768,
220 			.pixclock       = 15384,
221 			.left_margin    = 160,
222 			.right_margin   = 24,
223 			.upper_margin   = 29,
224 			.lower_margin   = 3,
225 			.hsync_len      = 136,
226 			.vsync_len      = 6,
227 			.sync           = FB_SYNC_EXT,
228 			.vmode          = FB_VMODE_NONINTERLACED
229 		}
230 	}
231 };
232 
233 size_t display_count = ARRAY_SIZE(displays);
234 
235 static int setup_display(void)
236 {
237 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
238 	int reg;
239 	int timeout = 100000;
240 
241 	enable_ipu_clock();
242 	imx_setup_hdmi();
243 
244 	/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
245 	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
246 
247 	reg = readl(&ccm->analog_pll_video);
248 	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
249 	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
250 	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
251 	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
252 	writel(reg, &ccm->analog_pll_video);
253 
254 	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
255 	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
256 
257 	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
258 	writel(reg, &ccm->analog_pll_video);
259 
260 	while (timeout--)
261 		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
262 			break;
263 	if (timeout < 0) {
264 		printf("Warning: video pll lock timeout!\n");
265 		return -ETIMEDOUT;
266 	}
267 
268 	reg = readl(&ccm->analog_pll_video);
269 	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
270 	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
271 	writel(reg, &ccm->analog_pll_video);
272 
273 	/* gate ipu1_di0_clk */
274 	clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
275 
276 	/* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
277 	reg = readl(&ccm->chsccdr);
278 	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
279 		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
280 		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
281 	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
282 	       (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
283 	       (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
284 	writel(reg, &ccm->chsccdr);
285 
286 	/* enable ipu1_di0_clk */
287 	setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
288 
289 	return 0;
290 }
291 #endif /* CONFIG_VIDEO_IPUV3 */
292 
293 #ifdef CONFIG_USB_EHCI_MX6
294 static void setup_usb(void)
295 {
296 	SETUP_IOMUX_PADS(usb_pads);
297 }
298 
299 int board_ehci_hcd_init(int port)
300 {
301 	if (port == 1)
302 		gpio_direction_output(USB_H1_VBUS, 1);
303 
304 	return 0;
305 }
306 #endif
307 
308 int board_early_init_f(void)
309 {
310 	int ret = 0;
311 	setup_iomux_uart();
312 
313 #ifdef CONFIG_VIDEO_IPUV3
314 	ret = setup_display();
315 #endif
316 
317 #ifdef CONFIG_USB_EHCI_MX6
318 	setup_usb();
319 #endif
320 	return ret;
321 }
322 
323 int board_init(void)
324 {
325 	/* address of boot parameters */
326 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
327 
328 	return 0;
329 }
330 
331 static bool is_hummingboard(void)
332 {
333 	int val1, val2;
334 
335 	SETUP_IOMUX_PADS(hb_cbi_sense);
336 
337 	gpio_direction_input(IMX_GPIO_NR(4, 9));
338 	gpio_direction_input(IMX_GPIO_NR(3, 4));
339 
340 	val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
341 	val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
342 
343 	/*
344 	 * Machine selection -
345 	 * Machine        val1, val2
346 	 * -------------------------
347 	 * HB rev 3.x     x     0
348 	 * CBi            0     1
349 	 * HB             1     1
350 	 */
351 
352 	if (val2 == 0)
353 		return true;
354 	else if (val1 == 0)
355 		return false;
356 	else
357 		return true;
358 }
359 
360 int checkboard(void)
361 {
362 	if (is_hummingboard())
363 		puts("Board: MX6 Hummingboard\n");
364 	else
365 		puts("Board: MX6 Cubox-i\n");
366 
367 	return 0;
368 }
369 
370 static bool is_mx6q(void)
371 {
372 	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
373 		return true;
374 	else
375 		return false;
376 }
377 
378 int board_late_init(void)
379 {
380 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
381 	if (is_hummingboard())
382 		setenv("board_name", "HUMMINGBOARD");
383 	else
384 		setenv("board_name", "CUBOXI");
385 
386 	if (is_mx6q())
387 		setenv("board_rev", "MX6Q");
388 	else
389 		setenv("board_rev", "MX6DL");
390 #endif
391 
392 	return 0;
393 }
394 
395 #ifdef CONFIG_SPL_BUILD
396 #include <asm/arch/mx6-ddr.h>
397 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
398 	.dram_sdclk_0 =  0x00020030,
399 	.dram_sdclk_1 =  0x00020030,
400 	.dram_cas =  0x00020030,
401 	.dram_ras =  0x00020030,
402 	.dram_reset =  0x00020030,
403 	.dram_sdcke0 =  0x00003000,
404 	.dram_sdcke1 =  0x00003000,
405 	.dram_sdba2 =  0x00000000,
406 	.dram_sdodt0 =  0x00003030,
407 	.dram_sdodt1 =  0x00003030,
408 	.dram_sdqs0 =  0x00000030,
409 	.dram_sdqs1 =  0x00000030,
410 	.dram_sdqs2 =  0x00000030,
411 	.dram_sdqs3 =  0x00000030,
412 	.dram_sdqs4 =  0x00000030,
413 	.dram_sdqs5 =  0x00000030,
414 	.dram_sdqs6 =  0x00000030,
415 	.dram_sdqs7 =  0x00000030,
416 	.dram_dqm0 =  0x00020030,
417 	.dram_dqm1 =  0x00020030,
418 	.dram_dqm2 =  0x00020030,
419 	.dram_dqm3 =  0x00020030,
420 	.dram_dqm4 =  0x00020030,
421 	.dram_dqm5 =  0x00020030,
422 	.dram_dqm6 =  0x00020030,
423 	.dram_dqm7 =  0x00020030,
424 };
425 
426 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
427 	.dram_sdclk_0 = 0x00000028,
428 	.dram_sdclk_1 = 0x00000028,
429 	.dram_cas =	0x00000028,
430 	.dram_ras =	0x00000028,
431 	.dram_reset =	0x000c0028,
432 	.dram_sdcke0 =	0x00003000,
433 	.dram_sdcke1 =	0x00003000,
434 	.dram_sdba2 =	0x00000000,
435 	.dram_sdodt0 =	0x00003030,
436 	.dram_sdodt1 =	0x00003030,
437 	.dram_sdqs0 =	0x00000028,
438 	.dram_sdqs1 =	0x00000028,
439 	.dram_sdqs2 =	0x00000028,
440 	.dram_sdqs3 =	0x00000028,
441 	.dram_sdqs4 =	0x00000028,
442 	.dram_sdqs5 =	0x00000028,
443 	.dram_sdqs6 =	0x00000028,
444 	.dram_sdqs7 =	0x00000028,
445 	.dram_dqm0 =	0x00000028,
446 	.dram_dqm1 =	0x00000028,
447 	.dram_dqm2 =	0x00000028,
448 	.dram_dqm3 =	0x00000028,
449 	.dram_dqm4 =	0x00000028,
450 	.dram_dqm5 =	0x00000028,
451 	.dram_dqm6 =	0x00000028,
452 	.dram_dqm7 =	0x00000028,
453 };
454 
455 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
456 	.grp_ddr_type =  0x000C0000,
457 	.grp_ddrmode_ctl =  0x00020000,
458 	.grp_ddrpke =  0x00000000,
459 	.grp_addds =  0x00000030,
460 	.grp_ctlds =  0x00000030,
461 	.grp_ddrmode =  0x00020000,
462 	.grp_b0ds =  0x00000030,
463 	.grp_b1ds =  0x00000030,
464 	.grp_b2ds =  0x00000030,
465 	.grp_b3ds =  0x00000030,
466 	.grp_b4ds =  0x00000030,
467 	.grp_b5ds =  0x00000030,
468 	.grp_b6ds =  0x00000030,
469 	.grp_b7ds =  0x00000030,
470 };
471 
472 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
473 	.grp_ddr_type = 0x000c0000,
474 	.grp_ddrmode_ctl = 0x00020000,
475 	.grp_ddrpke = 0x00000000,
476 	.grp_addds = 0x00000028,
477 	.grp_ctlds = 0x00000028,
478 	.grp_ddrmode = 0x00020000,
479 	.grp_b0ds = 0x00000028,
480 	.grp_b1ds = 0x00000028,
481 	.grp_b2ds = 0x00000028,
482 	.grp_b3ds = 0x00000028,
483 	.grp_b4ds = 0x00000028,
484 	.grp_b5ds = 0x00000028,
485 	.grp_b6ds = 0x00000028,
486 	.grp_b7ds = 0x00000028,
487 };
488 
489 /* microSOM with Dual processor and 1GB memory */
490 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
491 	.p0_mpwldectrl0 =  0x00000000,
492 	.p0_mpwldectrl1 =  0x00000000,
493 	.p1_mpwldectrl0 =  0x00000000,
494 	.p1_mpwldectrl1 =  0x00000000,
495 	.p0_mpdgctrl0 =    0x0314031c,
496 	.p0_mpdgctrl1 =    0x023e0304,
497 	.p1_mpdgctrl0 =    0x03240330,
498 	.p1_mpdgctrl1 =    0x03180260,
499 	.p0_mprddlctl =    0x3630323c,
500 	.p1_mprddlctl =    0x3436283a,
501 	.p0_mpwrdlctl =    0x36344038,
502 	.p1_mpwrdlctl =    0x422a423c,
503 };
504 
505 /* microSOM with Quad processor and 2GB memory */
506 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
507 	.p0_mpwldectrl0 =  0x00000000,
508 	.p0_mpwldectrl1 =  0x00000000,
509 	.p1_mpwldectrl0 =  0x00000000,
510 	.p1_mpwldectrl1 =  0x00000000,
511 	.p0_mpdgctrl0 =    0x0314031c,
512 	.p0_mpdgctrl1 =    0x023e0304,
513 	.p1_mpdgctrl0 =    0x03240330,
514 	.p1_mpdgctrl1 =    0x03180260,
515 	.p0_mprddlctl =    0x3630323c,
516 	.p1_mprddlctl =    0x3436283a,
517 	.p0_mpwrdlctl =    0x36344038,
518 	.p1_mpwrdlctl =    0x422a423c,
519 };
520 
521 /* microSOM with Solo processor and 512MB memory */
522 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
523 	.p0_mpwldectrl0 = 0x0045004D,
524 	.p0_mpwldectrl1 = 0x003A0047,
525 	.p0_mpdgctrl0 =   0x023C0224,
526 	.p0_mpdgctrl1 =   0x02000220,
527 	.p0_mprddlctl =   0x44444846,
528 	.p0_mpwrdlctl =   0x32343032,
529 };
530 
531 /* microSOM with Dual lite processor and 1GB memory */
532 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
533 	.p0_mpwldectrl0 =  0x0045004D,
534 	.p0_mpwldectrl1 =  0x003A0047,
535 	.p1_mpwldectrl0 =  0x001F001F,
536 	.p1_mpwldectrl1 =  0x00210035,
537 	.p0_mpdgctrl0 =    0x023C0224,
538 	.p0_mpdgctrl1 =    0x02000220,
539 	.p1_mpdgctrl0 =    0x02200220,
540 	.p1_mpdgctrl1 =    0x02040208,
541 	.p0_mprddlctl =    0x44444846,
542 	.p1_mprddlctl =    0x4042463C,
543 	.p0_mpwrdlctl =    0x32343032,
544 	.p1_mpwrdlctl =    0x36363430,
545 };
546 
547 static struct mx6_ddr3_cfg mem_ddr_2g = {
548 	.mem_speed = 1600,
549 	.density   = 2,
550 	.width     = 16,
551 	.banks     = 8,
552 	.rowaddr   = 14,
553 	.coladdr   = 10,
554 	.pagesz    = 2,
555 	.trcd      = 1375,
556 	.trcmin    = 4875,
557 	.trasmin   = 3500,
558 	.SRT       = 1,
559 };
560 
561 static struct mx6_ddr3_cfg mem_ddr_4g = {
562 	.mem_speed = 1600,
563 	.density = 4,
564 	.width = 16,
565 	.banks = 8,
566 	.rowaddr = 15,
567 	.coladdr = 10,
568 	.pagesz = 2,
569 	.trcd = 1375,
570 	.trcmin = 4875,
571 	.trasmin = 3500,
572 };
573 
574 static void ccgr_init(void)
575 {
576 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
577 
578 	writel(0x00C03F3F, &ccm->CCGR0);
579 	writel(0x0030FC03, &ccm->CCGR1);
580 	writel(0x0FFFC000, &ccm->CCGR2);
581 	writel(0x3FF00000, &ccm->CCGR3);
582 	writel(0x00FFF300, &ccm->CCGR4);
583 	writel(0x0F0000C3, &ccm->CCGR5);
584 	writel(0x000003FF, &ccm->CCGR6);
585 }
586 
587 static void gpr_init(void)
588 {
589 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
590 
591 	/* enable AXI cache for VDOA/VPU/IPU */
592 	writel(0xF00000CF, &iomux->gpr[4]);
593 	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
594 	writel(0x007F007F, &iomux->gpr[6]);
595 	writel(0x007F007F, &iomux->gpr[7]);
596 }
597 
598 static void spl_dram_init(int width)
599 {
600 	struct mx6_ddr_sysinfo sysinfo = {
601 		/* width of data bus: 0=16, 1=32, 2=64 */
602 		.dsize = width / 32,
603 		/* config for full 4GB range so that get_mem_size() works */
604 		.cs_density = 32,	/* 32Gb per CS */
605 		.ncs = 1,		/* single chip select */
606 		.cs1_mirror = 0,
607 		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
608 		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
609 		.walat = 1,	/* Write additional latency */
610 		.ralat = 5,	/* Read additional latency */
611 		.mif3_mode = 3,	/* Command prediction working mode */
612 		.bi_on = 1,	/* Bank interleaving enabled */
613 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
614 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
615 		.ddr_type = DDR_TYPE_DDR3,
616 	};
617 
618 	if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))
619 		mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
620 	else
621 		mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
622 
623 	if (is_cpu_type(MXC_CPU_MX6D))
624 		mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
625 	else if (is_cpu_type(MXC_CPU_MX6Q))
626 		mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
627 	else if (is_cpu_type(MXC_CPU_MX6DL))
628 		mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
629 	else if (is_cpu_type(MXC_CPU_MX6SOLO))
630 		mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
631 }
632 
633 void board_init_f(ulong dummy)
634 {
635 	/* setup AIPS and disable watchdog */
636 	arch_cpu_init();
637 
638 	ccgr_init();
639 	gpr_init();
640 
641 	/* iomux and setup of i2c */
642 	board_early_init_f();
643 
644 	/* setup GP timer */
645 	timer_init();
646 
647 	/* UART clocks enabled and gd valid - init serial console */
648 	preloader_console_init();
649 
650 	/* DDR initialization */
651 	if (is_cpu_type(MXC_CPU_MX6SOLO))
652 		spl_dram_init(32);
653 	else
654 		spl_dram_init(64);
655 
656 	/* Clear the BSS. */
657 	memset(__bss_start, 0, __bss_end - __bss_start);
658 
659 	/* load/boot image from boot device */
660 	board_init_r(NULL, 0);
661 }
662 #endif
663