1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> 7 * 8 * Based on SPL code from Solidrun tree, which is: 9 * Author: Tungyi Lin <tungyilin1127@gmail.com> 10 * 11 * Derived from EDM_CF_IMX6 code by TechNexion,Inc 12 * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <asm/arch/clock.h> 18 #include <asm/arch/imx-regs.h> 19 #include <asm/arch/iomux.h> 20 #include <asm/arch/mx6-pins.h> 21 #include <asm/arch/mxc_hdmi.h> 22 #include <linux/errno.h> 23 #include <asm/gpio.h> 24 #include <asm/mach-imx/iomux-v3.h> 25 #include <asm/mach-imx/sata.h> 26 #include <asm/mach-imx/video.h> 27 #include <mmc.h> 28 #include <fsl_esdhc.h> 29 #include <malloc.h> 30 #include <miiphy.h> 31 #include <netdev.h> 32 #include <asm/arch/crm_regs.h> 33 #include <asm/io.h> 34 #include <asm/arch/sys_proto.h> 35 #include <spl.h> 36 #include <usb.h> 37 #include <usb/ehci-ci.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 43 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 44 45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 46 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 47 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 48 49 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 51 52 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ 53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 54 55 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ 56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 57 58 #define ETH_PHY_RESET IMX_GPIO_NR(4, 15) 59 #define USB_H1_VBUS IMX_GPIO_NR(1, 0) 60 61 int dram_init(void) 62 { 63 gd->ram_size = imx_ddr_size(); 64 return 0; 65 } 66 67 static iomux_v3_cfg_t const uart1_pads[] = { 68 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 69 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 70 }; 71 72 static iomux_v3_cfg_t const usdhc2_pads[] = { 73 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 74 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 75 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 76 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 77 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 78 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 79 }; 80 81 static iomux_v3_cfg_t const hb_cbi_sense[] = { 82 /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ 83 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)), 84 IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), 85 }; 86 87 static iomux_v3_cfg_t const usb_pads[] = { 88 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 89 }; 90 91 static void setup_iomux_uart(void) 92 { 93 SETUP_IOMUX_PADS(uart1_pads); 94 } 95 96 static struct fsl_esdhc_cfg usdhc_cfg[1] = { 97 {USDHC2_BASE_ADDR}, 98 }; 99 100 int board_mmc_getcd(struct mmc *mmc) 101 { 102 return 1; /* uSDHC2 is always present */ 103 } 104 105 int board_mmc_init(bd_t *bis) 106 { 107 SETUP_IOMUX_PADS(usdhc2_pads); 108 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 109 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 110 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 111 112 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 113 } 114 115 static iomux_v3_cfg_t const enet_pads[] = { 116 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 117 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 118 /* AR8035 reset */ 119 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 120 /* AR8035 interrupt */ 121 IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), 122 /* GPIO16 -> AR8035 25MHz */ 123 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), 124 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)), 125 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 126 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 127 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 128 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 129 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 130 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 131 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)), 132 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 133 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 134 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 135 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 136 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 137 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 138 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 139 IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 140 }; 141 142 static void setup_iomux_enet(void) 143 { 144 SETUP_IOMUX_PADS(enet_pads); 145 146 gpio_direction_output(ETH_PHY_RESET, 0); 147 mdelay(10); 148 gpio_set_value(ETH_PHY_RESET, 1); 149 udelay(100); 150 } 151 152 int board_phy_config(struct phy_device *phydev) 153 { 154 if (phydev->drv->config) 155 phydev->drv->config(phydev); 156 157 return 0; 158 } 159 160 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */ 161 #define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4)) 162 163 int board_eth_init(bd_t *bis) 164 { 165 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 166 struct mii_dev *bus; 167 struct phy_device *phydev; 168 169 int ret = enable_fec_anatop_clock(0, ENET_25MHZ); 170 if (ret) 171 return ret; 172 173 /* set gpr1[ENET_CLK_SEL] */ 174 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); 175 176 setup_iomux_enet(); 177 178 bus = fec_get_miibus(IMX_FEC_BASE, -1); 179 if (!bus) 180 return -EINVAL; 181 182 phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII); 183 if (!phydev) { 184 ret = -EINVAL; 185 goto free_bus; 186 } 187 188 debug("using phy at address %d\n", phydev->addr); 189 ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); 190 if (ret) 191 goto free_phydev; 192 193 return 0; 194 195 free_phydev: 196 free(phydev); 197 free_bus: 198 free(bus); 199 return ret; 200 } 201 202 #ifdef CONFIG_VIDEO_IPUV3 203 static void do_enable_hdmi(struct display_info_t const *dev) 204 { 205 imx_enable_hdmi_phy(); 206 } 207 208 struct display_info_t const displays[] = { 209 { 210 .bus = -1, 211 .addr = 0, 212 .pixfmt = IPU_PIX_FMT_RGB24, 213 .detect = detect_hdmi, 214 .enable = do_enable_hdmi, 215 .mode = { 216 .name = "HDMI", 217 /* 1024x768@60Hz (VESA)*/ 218 .refresh = 60, 219 .xres = 1024, 220 .yres = 768, 221 .pixclock = 15384, 222 .left_margin = 160, 223 .right_margin = 24, 224 .upper_margin = 29, 225 .lower_margin = 3, 226 .hsync_len = 136, 227 .vsync_len = 6, 228 .sync = FB_SYNC_EXT, 229 .vmode = FB_VMODE_NONINTERLACED 230 } 231 } 232 }; 233 234 size_t display_count = ARRAY_SIZE(displays); 235 236 static int setup_display(void) 237 { 238 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 239 int reg; 240 int timeout = 100000; 241 242 enable_ipu_clock(); 243 imx_setup_hdmi(); 244 245 /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ 246 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); 247 248 reg = readl(&ccm->analog_pll_video); 249 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; 250 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); 251 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; 252 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); 253 writel(reg, &ccm->analog_pll_video); 254 255 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); 256 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); 257 258 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; 259 writel(reg, &ccm->analog_pll_video); 260 261 while (timeout--) 262 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) 263 break; 264 if (timeout < 0) { 265 printf("Warning: video pll lock timeout!\n"); 266 return -ETIMEDOUT; 267 } 268 269 reg = readl(&ccm->analog_pll_video); 270 reg |= BM_ANADIG_PLL_VIDEO_ENABLE; 271 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; 272 writel(reg, &ccm->analog_pll_video); 273 274 /* gate ipu1_di0_clk */ 275 clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); 276 277 /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ 278 reg = readl(&ccm->chsccdr); 279 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | 280 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | 281 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 282 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | 283 (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | 284 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 285 writel(reg, &ccm->chsccdr); 286 287 /* enable ipu1_di0_clk */ 288 setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); 289 290 return 0; 291 } 292 #endif /* CONFIG_VIDEO_IPUV3 */ 293 294 #ifdef CONFIG_USB_EHCI_MX6 295 static void setup_usb(void) 296 { 297 SETUP_IOMUX_PADS(usb_pads); 298 } 299 300 int board_ehci_hcd_init(int port) 301 { 302 if (port == 1) 303 gpio_direction_output(USB_H1_VBUS, 1); 304 305 return 0; 306 } 307 #endif 308 309 int board_early_init_f(void) 310 { 311 int ret = 0; 312 setup_iomux_uart(); 313 314 #ifdef CONFIG_VIDEO_IPUV3 315 ret = setup_display(); 316 #endif 317 318 #ifdef CONFIG_CMD_SATA 319 setup_sata(); 320 #endif 321 322 #ifdef CONFIG_USB_EHCI_MX6 323 setup_usb(); 324 #endif 325 return ret; 326 } 327 328 int board_init(void) 329 { 330 /* address of boot parameters */ 331 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 332 333 return 0; 334 } 335 336 static bool is_hummingboard(void) 337 { 338 int val1, val2; 339 340 SETUP_IOMUX_PADS(hb_cbi_sense); 341 342 gpio_direction_input(IMX_GPIO_NR(4, 9)); 343 gpio_direction_input(IMX_GPIO_NR(3, 4)); 344 345 val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); 346 val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); 347 348 /* 349 * Machine selection - 350 * Machine val1, val2 351 * ------------------------- 352 * HB rev 3.x x 0 353 * CBi 0 1 354 * HB 1 1 355 */ 356 357 if (val2 == 0) 358 return true; 359 else if (val1 == 0) 360 return false; 361 else 362 return true; 363 } 364 365 int checkboard(void) 366 { 367 if (is_hummingboard()) 368 puts("Board: MX6 Hummingboard\n"); 369 else 370 puts("Board: MX6 Cubox-i\n"); 371 372 return 0; 373 } 374 375 int board_late_init(void) 376 { 377 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 378 if (is_hummingboard()) 379 setenv("board_name", "HUMMINGBOARD"); 380 else 381 setenv("board_name", "CUBOXI"); 382 383 if (is_mx6dq()) 384 setenv("board_rev", "MX6Q"); 385 else 386 setenv("board_rev", "MX6DL"); 387 #endif 388 389 return 0; 390 } 391 392 #ifdef CONFIG_SPL_BUILD 393 #include <asm/arch/mx6-ddr.h> 394 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { 395 .dram_sdclk_0 = 0x00020030, 396 .dram_sdclk_1 = 0x00020030, 397 .dram_cas = 0x00020030, 398 .dram_ras = 0x00020030, 399 .dram_reset = 0x00020030, 400 .dram_sdcke0 = 0x00003000, 401 .dram_sdcke1 = 0x00003000, 402 .dram_sdba2 = 0x00000000, 403 .dram_sdodt0 = 0x00003030, 404 .dram_sdodt1 = 0x00003030, 405 .dram_sdqs0 = 0x00000030, 406 .dram_sdqs1 = 0x00000030, 407 .dram_sdqs2 = 0x00000030, 408 .dram_sdqs3 = 0x00000030, 409 .dram_sdqs4 = 0x00000030, 410 .dram_sdqs5 = 0x00000030, 411 .dram_sdqs6 = 0x00000030, 412 .dram_sdqs7 = 0x00000030, 413 .dram_dqm0 = 0x00020030, 414 .dram_dqm1 = 0x00020030, 415 .dram_dqm2 = 0x00020030, 416 .dram_dqm3 = 0x00020030, 417 .dram_dqm4 = 0x00020030, 418 .dram_dqm5 = 0x00020030, 419 .dram_dqm6 = 0x00020030, 420 .dram_dqm7 = 0x00020030, 421 }; 422 423 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = { 424 .dram_sdclk_0 = 0x00000028, 425 .dram_sdclk_1 = 0x00000028, 426 .dram_cas = 0x00000028, 427 .dram_ras = 0x00000028, 428 .dram_reset = 0x000c0028, 429 .dram_sdcke0 = 0x00003000, 430 .dram_sdcke1 = 0x00003000, 431 .dram_sdba2 = 0x00000000, 432 .dram_sdodt0 = 0x00003030, 433 .dram_sdodt1 = 0x00003030, 434 .dram_sdqs0 = 0x00000028, 435 .dram_sdqs1 = 0x00000028, 436 .dram_sdqs2 = 0x00000028, 437 .dram_sdqs3 = 0x00000028, 438 .dram_sdqs4 = 0x00000028, 439 .dram_sdqs5 = 0x00000028, 440 .dram_sdqs6 = 0x00000028, 441 .dram_sdqs7 = 0x00000028, 442 .dram_dqm0 = 0x00000028, 443 .dram_dqm1 = 0x00000028, 444 .dram_dqm2 = 0x00000028, 445 .dram_dqm3 = 0x00000028, 446 .dram_dqm4 = 0x00000028, 447 .dram_dqm5 = 0x00000028, 448 .dram_dqm6 = 0x00000028, 449 .dram_dqm7 = 0x00000028, 450 }; 451 452 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = { 453 .grp_ddr_type = 0x000C0000, 454 .grp_ddrmode_ctl = 0x00020000, 455 .grp_ddrpke = 0x00000000, 456 .grp_addds = 0x00000030, 457 .grp_ctlds = 0x00000030, 458 .grp_ddrmode = 0x00020000, 459 .grp_b0ds = 0x00000030, 460 .grp_b1ds = 0x00000030, 461 .grp_b2ds = 0x00000030, 462 .grp_b3ds = 0x00000030, 463 .grp_b4ds = 0x00000030, 464 .grp_b5ds = 0x00000030, 465 .grp_b6ds = 0x00000030, 466 .grp_b7ds = 0x00000030, 467 }; 468 469 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 470 .grp_ddr_type = 0x000c0000, 471 .grp_ddrmode_ctl = 0x00020000, 472 .grp_ddrpke = 0x00000000, 473 .grp_addds = 0x00000028, 474 .grp_ctlds = 0x00000028, 475 .grp_ddrmode = 0x00020000, 476 .grp_b0ds = 0x00000028, 477 .grp_b1ds = 0x00000028, 478 .grp_b2ds = 0x00000028, 479 .grp_b3ds = 0x00000028, 480 .grp_b4ds = 0x00000028, 481 .grp_b5ds = 0x00000028, 482 .grp_b6ds = 0x00000028, 483 .grp_b7ds = 0x00000028, 484 }; 485 486 /* microSOM with Dual processor and 1GB memory */ 487 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = { 488 .p0_mpwldectrl0 = 0x00000000, 489 .p0_mpwldectrl1 = 0x00000000, 490 .p1_mpwldectrl0 = 0x00000000, 491 .p1_mpwldectrl1 = 0x00000000, 492 .p0_mpdgctrl0 = 0x0314031c, 493 .p0_mpdgctrl1 = 0x023e0304, 494 .p1_mpdgctrl0 = 0x03240330, 495 .p1_mpdgctrl1 = 0x03180260, 496 .p0_mprddlctl = 0x3630323c, 497 .p1_mprddlctl = 0x3436283a, 498 .p0_mpwrdlctl = 0x36344038, 499 .p1_mpwrdlctl = 0x422a423c, 500 }; 501 502 /* microSOM with Quad processor and 2GB memory */ 503 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = { 504 .p0_mpwldectrl0 = 0x00000000, 505 .p0_mpwldectrl1 = 0x00000000, 506 .p1_mpwldectrl0 = 0x00000000, 507 .p1_mpwldectrl1 = 0x00000000, 508 .p0_mpdgctrl0 = 0x0314031c, 509 .p0_mpdgctrl1 = 0x023e0304, 510 .p1_mpdgctrl0 = 0x03240330, 511 .p1_mpdgctrl1 = 0x03180260, 512 .p0_mprddlctl = 0x3630323c, 513 .p1_mprddlctl = 0x3436283a, 514 .p0_mpwrdlctl = 0x36344038, 515 .p1_mpwrdlctl = 0x422a423c, 516 }; 517 518 /* microSOM with Solo processor and 512MB memory */ 519 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = { 520 .p0_mpwldectrl0 = 0x0045004D, 521 .p0_mpwldectrl1 = 0x003A0047, 522 .p0_mpdgctrl0 = 0x023C0224, 523 .p0_mpdgctrl1 = 0x02000220, 524 .p0_mprddlctl = 0x44444846, 525 .p0_mpwrdlctl = 0x32343032, 526 }; 527 528 /* microSOM with Dual lite processor and 1GB memory */ 529 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = { 530 .p0_mpwldectrl0 = 0x0045004D, 531 .p0_mpwldectrl1 = 0x003A0047, 532 .p1_mpwldectrl0 = 0x001F001F, 533 .p1_mpwldectrl1 = 0x00210035, 534 .p0_mpdgctrl0 = 0x023C0224, 535 .p0_mpdgctrl1 = 0x02000220, 536 .p1_mpdgctrl0 = 0x02200220, 537 .p1_mpdgctrl1 = 0x02040208, 538 .p0_mprddlctl = 0x44444846, 539 .p1_mprddlctl = 0x4042463C, 540 .p0_mpwrdlctl = 0x32343032, 541 .p1_mpwrdlctl = 0x36363430, 542 }; 543 544 static struct mx6_ddr3_cfg mem_ddr_2g = { 545 .mem_speed = 1600, 546 .density = 2, 547 .width = 16, 548 .banks = 8, 549 .rowaddr = 14, 550 .coladdr = 10, 551 .pagesz = 2, 552 .trcd = 1375, 553 .trcmin = 4875, 554 .trasmin = 3500, 555 .SRT = 1, 556 }; 557 558 static struct mx6_ddr3_cfg mem_ddr_4g = { 559 .mem_speed = 1600, 560 .density = 4, 561 .width = 16, 562 .banks = 8, 563 .rowaddr = 15, 564 .coladdr = 10, 565 .pagesz = 2, 566 .trcd = 1375, 567 .trcmin = 4875, 568 .trasmin = 3500, 569 }; 570 571 static void ccgr_init(void) 572 { 573 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 574 575 writel(0x00C03F3F, &ccm->CCGR0); 576 writel(0x0030FC03, &ccm->CCGR1); 577 writel(0x0FFFC000, &ccm->CCGR2); 578 writel(0x3FF00000, &ccm->CCGR3); 579 writel(0x00FFF300, &ccm->CCGR4); 580 writel(0x0F0000C3, &ccm->CCGR5); 581 writel(0x000003FF, &ccm->CCGR6); 582 } 583 584 static void gpr_init(void) 585 { 586 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 587 588 /* enable AXI cache for VDOA/VPU/IPU */ 589 writel(0xF00000CF, &iomux->gpr[4]); 590 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 591 writel(0x007F007F, &iomux->gpr[6]); 592 writel(0x007F007F, &iomux->gpr[7]); 593 } 594 595 static void spl_dram_init(int width) 596 { 597 struct mx6_ddr_sysinfo sysinfo = { 598 /* width of data bus: 0=16, 1=32, 2=64 */ 599 .dsize = width / 32, 600 /* config for full 4GB range so that get_mem_size() works */ 601 .cs_density = 32, /* 32Gb per CS */ 602 .ncs = 1, /* single chip select */ 603 .cs1_mirror = 0, 604 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 605 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 606 .walat = 1, /* Write additional latency */ 607 .ralat = 5, /* Read additional latency */ 608 .mif3_mode = 3, /* Command prediction working mode */ 609 .bi_on = 1, /* Bank interleaving enabled */ 610 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 611 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 612 .ddr_type = DDR_TYPE_DDR3, 613 .refsel = 1, /* Refresh cycles at 32KHz */ 614 .refr = 7, /* 8 refresh commands per refresh cycle */ 615 }; 616 617 if (is_mx6dq()) 618 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); 619 else 620 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); 621 622 if (is_cpu_type(MXC_CPU_MX6D)) 623 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); 624 else if (is_cpu_type(MXC_CPU_MX6Q)) 625 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); 626 else if (is_cpu_type(MXC_CPU_MX6DL)) 627 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g); 628 else if (is_cpu_type(MXC_CPU_MX6SOLO)) 629 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g); 630 } 631 632 void board_init_f(ulong dummy) 633 { 634 /* setup AIPS and disable watchdog */ 635 arch_cpu_init(); 636 637 ccgr_init(); 638 gpr_init(); 639 640 /* iomux and setup of i2c */ 641 board_early_init_f(); 642 643 /* setup GP timer */ 644 timer_init(); 645 646 /* UART clocks enabled and gd valid - init serial console */ 647 preloader_console_init(); 648 649 /* DDR initialization */ 650 if (is_cpu_type(MXC_CPU_MX6SOLO)) 651 spl_dram_init(32); 652 else 653 spl_dram_init(64); 654 655 /* Clear the BSS. */ 656 memset(__bss_start, 0, __bss_end - __bss_start); 657 658 /* load/boot image from boot device */ 659 board_init_r(NULL, 0); 660 } 661 #endif 662