1 /*
2  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <miiphy.h>
10 #include <netdev.h>
11 #include <asm/io.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 
15 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
16 #include <../serdes/a38x/high_speed_env_spec.h>
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 #define ETH_PHY_CTRL_REG		0
21 #define ETH_PHY_CTRL_POWER_DOWN_BIT	11
22 #define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
23 
24 /*
25  * Those values and defines are taken from the Marvell U-Boot version
26  * "u-boot-2013.01-15t1-clearfog"
27  */
28 #define BOARD_GPP_OUT_ENA_LOW	0xffffffff
29 #define BOARD_GPP_OUT_ENA_MID	0xffffffff
30 
31 #define BOARD_GPP_OUT_VAL_LOW	0x0
32 #define BOARD_GPP_OUT_VAL_MID	0x0
33 #define BOARD_GPP_POL_LOW	0x0
34 #define BOARD_GPP_POL_MID	0x0
35 
36 /* IO expander on Marvell GP board includes e.g. fan enabling */
37 struct marvell_io_exp {
38 	u8 chip;
39 	u8 addr;
40 	u8 val;
41 };
42 
43 static struct marvell_io_exp io_exp[] = {
44 	{ 0x20, 2, 0x40 },	/* Deassert both mini pcie reset signals */
45 	{ 0x20, 6, 0xf9 },
46 	{ 0x20, 2, 0x46 },	/* rst signals and ena USB3 current limiter */
47 	{ 0x20, 6, 0xb9 },
48 	{ 0x20, 3, 0x00 },	/* Set SFP_TX_DIS to zero */
49 	{ 0x20, 7, 0xbf },	/* Drive SFP_TX_DIS to zero */
50 };
51 
52 static struct serdes_map board_serdes_map[] = {
53 	{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
54 	{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
55 	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
56 	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
57 	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
58 	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
59 };
60 
61 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
62 {
63 	*serdes_map_array = board_serdes_map;
64 	*count = ARRAY_SIZE(board_serdes_map);
65 	return 0;
66 }
67 
68 /*
69  * Define the DDR layout / topology here in the board file. This will
70  * be used by the DDR3 init code in the SPL U-Boot version to configure
71  * the DDR3 controller.
72  */
73 static struct hws_topology_map board_topology_map = {
74 	0x1, /* active interfaces */
75 	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
76 	{ { { {0x1, 0, 0, 0},
77 	      {0x1, 0, 0, 0},
78 	      {0x1, 0, 0, 0},
79 	      {0x1, 0, 0, 0},
80 	      {0x1, 0, 0, 0} },
81 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
82 	    BUS_WIDTH_16,		/* memory_width */
83 	    MEM_4G,			/* mem_size */
84 	    DDR_FREQ_800,		/* frequency */
85 	    0, 0,			/* cas_wl cas_l */
86 	    HWS_TEMP_LOW,		/* temperature */
87 	    HWS_TIM_DEFAULT} },		/* timing */
88 	5,				/* Num Of Bus Per Interface*/
89 	BUS_MASK_32BIT			/* Busses mask */
90 };
91 
92 struct hws_topology_map *ddr3_get_topology_map(void)
93 {
94 	/* Return the board topology as defined in the board code */
95 	return &board_topology_map;
96 }
97 
98 int board_early_init_f(void)
99 {
100 	/* Configure MPP */
101 	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
102 	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
103 	writel(0x10400011, MVEBU_MPP_BASE + 0x08);
104 	writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
105 	writel(0x44400002, MVEBU_MPP_BASE + 0x10);
106 	writel(0x41144004, MVEBU_MPP_BASE + 0x14);
107 	writel(0x40333333, MVEBU_MPP_BASE + 0x18);
108 	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
109 
110 	/* Set GPP Out value */
111 	writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
112 	writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
113 
114 	/* Set GPP Polarity */
115 	writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
116 	writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
117 
118 	/* Set GPP Out Enable */
119 	writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
120 	writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
121 
122 	return 0;
123 }
124 
125 int board_init(void)
126 {
127 	int i;
128 
129 	/* Address of boot parameters */
130 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
131 
132 	/* Toggle GPIO41 to reset onboard switch and phy */
133 	clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
134 	clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
135 	/* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
136 	clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
137 	clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
138 	mdelay(1);
139 	setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
140 	setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
141 	mdelay(10);
142 
143 	/* Init I2C IO expanders */
144 	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
145 		i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
146 
147 	return 0;
148 }
149 
150 int checkboard(void)
151 {
152 	puts("Board: SolidRun ClearFog\n");
153 
154 	return 0;
155 }
156 
157 int board_eth_init(bd_t *bis)
158 {
159 	cpu_eth_init(bis); /* Built in controller(s) come first */
160 	return pci_eth_init(bis);
161 }
162