1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Copyright 2008 Freescale Semiconductor, Inc. 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <asm/mmu.h> 31 32 struct fsl_e_tlb_entry tlb_table[] = { 33 /* TLB 0 - for temp stack in cache */ 34 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 35 MAS3_SX|MAS3_SW|MAS3_SR, 0, 36 0, 0, BOOKE_PAGESZ_4K, 0), 37 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 38 MAS3_SX|MAS3_SW|MAS3_SR, 0, 39 0, 0, BOOKE_PAGESZ_4K, 0), 40 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 41 MAS3_SX|MAS3_SW|MAS3_SR, 0, 42 0, 0, BOOKE_PAGESZ_4K, 0), 43 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44 MAS3_SX|MAS3_SW|MAS3_SR, 0, 45 0, 0, BOOKE_PAGESZ_4K, 0), 46 47 48 /* 49 * TLB 1: 64M Non-cacheable, guarded 50 * 0xfc000000 64M FLASH 51 * Out of reset this entry is only 4K. 52 */ 53 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, 54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55 0, 1, BOOKE_PAGESZ_64M, 1), 56 57 /* 58 * TLB 2: 256M Non-cacheable, guarded 59 * 0x80000000 256M PCI1 MEM First half 60 */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, 62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63 0, 2, BOOKE_PAGESZ_256M, 1), 64 65 /* 66 * TLB 3: 256M Non-cacheable, guarded 67 * 0x90000000 256M PCI1 MEM Second half 68 */ 69 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, 70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71 0, 3, BOOKE_PAGESZ_256M, 1), 72 73 #if defined(CONFIG_SYS_FPGA_BASE) 74 /* 75 * TLB 4: 1M Non-cacheable, guarded 76 * 0xc0000000 1M FPGA and NAND 77 */ 78 SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, 79 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 80 0, 4, BOOKE_PAGESZ_1M, 1), 81 #endif 82 83 /* 84 * TLB 5: 64M Non-cacheable, guarded 85 * 0xc8000000 16M LIME GDC framebuffer 86 * 0xc9fc0000 256K LIME GDC MMIO 87 * (0xcbfc0000 256K LIME GDC MMIO) 88 * MMIO is relocatable and could be at 0xcbfc0000 89 */ 90 SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, 91 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 92 0, 5, BOOKE_PAGESZ_64M, 1), 93 94 /* 95 * TLB 6: 64M Non-cacheable, guarded 96 * 0xe000_0000 1M CCSRBAR 97 * 0xe200_0000 16M PCI1 IO 98 */ 99 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 100 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 101 0, 6, BOOKE_PAGESZ_64M, 1), 102 103 #if !defined(CONFIG_SPD_EEPROM) 104 /* 105 * TLB 7+8: 512M DDR, cache disabled (needed for memory test) 106 * 0x00000000 512M DDR System memory 107 * Without SPD EEPROM configured DDR, this must be setup manually. 108 * Make sure the TLB count at the top of this table is correct. 109 * Likely it needs to be increased by two for these entries. 110 */ 111 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 112 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 113 0, 7, BOOKE_PAGESZ_256M, 1), 114 115 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 116 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 117 0, 8, BOOKE_PAGESZ_256M, 1), 118 #endif 119 }; 120 121 int num_tlb_entries = ARRAY_SIZE(tlb_table); 122