1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Copyright 2008 Freescale Semiconductor, Inc. 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/mmu.h> 15 16 struct fsl_e_tlb_entry tlb_table[] = { 17 /* TLB 0 - for temp stack in cache */ 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 19 MAS3_SX|MAS3_SW|MAS3_SR, 0, 20 0, 0, BOOKE_PAGESZ_4K, 0), 21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28 MAS3_SX|MAS3_SW|MAS3_SR, 0, 29 0, 0, BOOKE_PAGESZ_4K, 0), 30 31 32 /* 33 * TLB 1: 64M Non-cacheable, guarded 34 * 0xfc000000 64M FLASH 35 * Out of reset this entry is only 4K. 36 */ 37 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, 38 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39 0, 1, BOOKE_PAGESZ_64M, 1), 40 41 /* 42 * TLB 2: 256M Non-cacheable, guarded 43 * 0x80000000 256M PCI1 MEM First half 44 */ 45 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, 46 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 47 0, 2, BOOKE_PAGESZ_256M, 1), 48 49 /* 50 * TLB 3: 256M Non-cacheable, guarded 51 * 0x90000000 256M PCI1 MEM Second half 52 */ 53 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, 54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55 0, 3, BOOKE_PAGESZ_256M, 1), 56 57 #if defined(CONFIG_SYS_FPGA_BASE) 58 /* 59 * TLB 4: 1M Non-cacheable, guarded 60 * 0xc0000000 1M FPGA and NAND 61 */ 62 SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, 63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64 0, 4, BOOKE_PAGESZ_1M, 1), 65 #endif 66 67 /* 68 * TLB 5: 64M Non-cacheable, guarded 69 * 0xc8000000 16M LIME GDC framebuffer 70 * 0xc9fc0000 256K LIME GDC MMIO 71 * (0xcbfc0000 256K LIME GDC MMIO) 72 * MMIO is relocatable and could be at 0xcbfc0000 73 */ 74 SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, 75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 76 0, 5, BOOKE_PAGESZ_64M, 1), 77 78 /* 79 * TLB 6: 64M Non-cacheable, guarded 80 * 0xe000_0000 1M CCSRBAR 81 * 0xe200_0000 16M PCI1 IO 82 */ 83 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 84 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 85 0, 6, BOOKE_PAGESZ_64M, 1), 86 87 #if !defined(CONFIG_SPD_EEPROM) 88 /* 89 * TLB 7+8: 512M DDR, cache disabled (needed for memory test) 90 * 0x00000000 512M DDR System memory 91 * Without SPD EEPROM configured DDR, this must be setup manually. 92 * Make sure the TLB count at the top of this table is correct. 93 * Likely it needs to be increased by two for these entries. 94 */ 95 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 96 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97 0, 7, BOOKE_PAGESZ_256M, 1), 98 99 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 100 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 101 0, 8, BOOKE_PAGESZ_256M, 1), 102 #endif 103 }; 104 105 int num_tlb_entries = ARRAY_SIZE(tlb_table); 106