1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Copyright 2004 Freescale Semiconductor. 6 * (C) Copyright 2002,2003, Motorola Inc. 7 * Xianghua Xiao, (X.Xiao@motorola.com) 8 * 9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #include <common.h> 31 #include <pci.h> 32 #include <asm/processor.h> 33 #include <asm/immap_85xx.h> 34 #include <ioports.h> 35 #include <flash.h> 36 #include <libfdt.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 #include <i2c.h> 40 #include <mb862xx.h> 41 #include <video_fb.h> 42 #include "upm_table.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 extern flash_info_t flash_info[]; /* FLASH chips info */ 47 extern GraphicDevice mb862xx; 48 49 void local_bus_init (void); 50 ulong flash_get_size (ulong base, int banknum); 51 52 int checkboard (void) 53 { 54 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 55 char buf[64]; 56 int f; 57 int i = getenv_f("serial#", buf, sizeof(buf)); 58 #ifdef CONFIG_PCI 59 char *src; 60 #endif 61 62 puts("Board: Socrates"); 63 if (i > 0) { 64 puts(", serial# "); 65 puts(buf); 66 } 67 putc('\n'); 68 69 #ifdef CONFIG_PCI 70 /* Check the PCI_clk sel bit */ 71 if (in_be32(&gur->porpllsr) & (1<<15)) { 72 src = "SYSCLK"; 73 f = CONFIG_SYS_CLK_FREQ; 74 } else { 75 src = "PCI_CLK"; 76 f = CONFIG_PCI_CLK_FREQ; 77 } 78 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); 79 #else 80 printf ("PCI1: disabled\n"); 81 #endif 82 83 /* 84 * Initialize local bus. 85 */ 86 local_bus_init (); 87 return 0; 88 } 89 90 int misc_init_r (void) 91 { 92 /* 93 * Adjust flash start and offset to detected values 94 */ 95 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; 96 gd->bd->bi_flashoffset = 0; 97 98 /* 99 * Check if boot FLASH isn't max size 100 */ 101 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { 102 set_lbc_or(0, gd->bd->bi_flashstart | 103 (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); 104 set_lbc_br(0, gd->bd->bi_flashstart | 105 (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); 106 107 /* 108 * Re-check to get correct base address 109 */ 110 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); 111 } 112 113 /* 114 * Check if only one FLASH bank is available 115 */ 116 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { 117 set_lbc_or(1, 0); 118 set_lbc_br(1, 0); 119 120 /* 121 * Re-do flash protection upon new addresses 122 */ 123 flash_protect (FLAG_PROTECT_CLEAR, 124 gd->bd->bi_flashstart, 0xffffffff, 125 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); 126 127 /* Monitor protection ON by default */ 128 flash_protect (FLAG_PROTECT_SET, 129 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, 130 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); 131 132 /* Environment protection ON by default */ 133 flash_protect (FLAG_PROTECT_SET, 134 CONFIG_ENV_ADDR, 135 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, 136 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); 137 138 /* Redundant environment protection ON by default */ 139 flash_protect (FLAG_PROTECT_SET, 140 CONFIG_ENV_ADDR_REDUND, 141 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, 142 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); 143 } 144 145 return 0; 146 } 147 148 /* 149 * Initialize Local Bus 150 */ 151 void local_bus_init (void) 152 { 153 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 154 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 155 sys_info_t sysinfo; 156 uint clkdiv; 157 uint lbc_mhz; 158 uint lcrr = CONFIG_SYS_LBC_LCRR; 159 160 get_sys_info (&sysinfo); 161 clkdiv = lbc->lcrr & LCRR_CLKDIV; 162 lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; 163 164 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ 165 if (lbc_mhz >= 66) 166 lcrr &= ~LCRR_DBYP; /* DLL Enabled */ 167 else 168 lcrr |= LCRR_DBYP; /* DLL Bypass */ 169 170 out_be32 (&lbc->lcrr, lcrr); 171 asm ("sync;isync;msync"); 172 173 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ 174 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ 175 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ 176 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ 177 178 /* Init UPMA for FPGA access */ 179 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ 180 upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); 181 182 /* Init UPMB for Lime controller access */ 183 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ 184 upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); 185 } 186 187 #if defined(CONFIG_PCI) 188 /* 189 * Initialize PCI Devices, report devices found. 190 */ 191 192 #ifndef CONFIG_PCI_PNP 193 static struct pci_config_table pci_mpc85xxads_config_table[] = { 194 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 195 PCI_IDSEL_NUMBER, PCI_ANY_ID, 196 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 197 PCI_ENET0_MEMADDR, 198 PCI_COMMAND_MEMORY | 199 PCI_COMMAND_MASTER}}, 200 {} 201 }; 202 #endif 203 204 205 static struct pci_controller hose = { 206 #ifndef CONFIG_PCI_PNP 207 config_table:pci_mpc85xxads_config_table, 208 #endif 209 }; 210 211 #endif /* CONFIG_PCI */ 212 213 214 void pci_init_board (void) 215 { 216 #ifdef CONFIG_PCI 217 pci_mpc85xx_init (&hose); 218 #endif /* CONFIG_PCI */ 219 } 220 221 #ifdef CONFIG_BOARD_EARLY_INIT_R 222 int board_early_init_r (void) 223 { 224 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 225 226 /* set and reset the GPIO pin 2 which will reset the W83782G chip */ 227 out_8((unsigned char*)&gur->gpoutdr, 0x3F ); 228 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ 229 udelay(200); 230 out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); 231 232 return (0); 233 } 234 #endif /* CONFIG_BOARD_EARLY_INIT_R */ 235 236 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 237 void 238 ft_board_setup(void *blob, bd_t *bd) 239 { 240 u32 val[12]; 241 int rc, i = 0; 242 243 ft_cpu_setup(blob, bd); 244 245 /* Fixup NOR FLASH mapping */ 246 val[i++] = 0; /* chip select number */ 247 val[i++] = 0; /* always 0 */ 248 val[i++] = gd->bd->bi_flashstart; 249 val[i++] = gd->bd->bi_flashsize; 250 251 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { 252 /* Fixup LIME mapping */ 253 val[i++] = 2; /* chip select number */ 254 val[i++] = 0; /* always 0 */ 255 val[i++] = CONFIG_SYS_LIME_BASE; 256 val[i++] = CONFIG_SYS_LIME_SIZE; 257 } 258 259 /* Fixup FPGA mapping */ 260 val[i++] = 3; /* chip select number */ 261 val[i++] = 0; /* always 0 */ 262 val[i++] = CONFIG_SYS_FPGA_BASE; 263 val[i++] = CONFIG_SYS_FPGA_SIZE; 264 265 rc = fdt_find_and_setprop(blob, "/localbus", "ranges", 266 val, i * sizeof(u32), 1); 267 if (rc) 268 printf("Unable to update localbus ranges, err=%s\n", 269 fdt_strerror(rc)); 270 } 271 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ 272 273 #define DEFAULT_BRIGHTNESS 25 274 #define BACKLIGHT_ENABLE (1 << 31) 275 276 static const gdc_regs init_regs [] = 277 { 278 {0x0100, 0x00010f00}, 279 {0x0020, 0x801901df}, 280 {0x0024, 0x00000000}, 281 {0x0028, 0x00000000}, 282 {0x002c, 0x00000000}, 283 {0x0110, 0x00000000}, 284 {0x0114, 0x00000000}, 285 {0x0118, 0x01df0320}, 286 {0x0004, 0x041f0000}, 287 {0x0008, 0x031f031f}, 288 {0x000c, 0x017f0349}, 289 {0x0010, 0x020c0000}, 290 {0x0014, 0x01df01e9}, 291 {0x0018, 0x00000000}, 292 {0x001c, 0x01e00320}, 293 {0x0100, 0x80010f00}, 294 {0x0, 0x0} 295 }; 296 297 const gdc_regs *board_get_regs (void) 298 { 299 return init_regs; 300 } 301 302 int lime_probe(void) 303 { 304 uint cfg_br2; 305 uint cfg_or2; 306 int type; 307 308 cfg_br2 = get_lbc_br(2); 309 cfg_or2 = get_lbc_or(2); 310 311 /* Configure GPCM for CS2 */ 312 set_lbc_br(2, 0); 313 set_lbc_or(2, 0xfc000410); 314 set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901); 315 316 /* Get controller type */ 317 type = mb862xx_probe(CONFIG_SYS_LIME_BASE); 318 319 /* Restore previous CS2 configuration */ 320 set_lbc_br(2, 0); 321 set_lbc_or(2, cfg_or2); 322 set_lbc_br(2, cfg_br2); 323 324 return (type == MB862XX_TYPE_LIME) ? 1 : 0; 325 } 326 327 /* Returns Lime base address */ 328 unsigned int board_video_init (void) 329 { 330 if (!lime_probe()) 331 return 0; 332 333 mb862xx.winSizeX = 800; 334 mb862xx.winSizeY = 480; 335 mb862xx.gdfIndex = GDF_15BIT_555RGB; 336 mb862xx.gdfBytesPP = 2; 337 338 return CONFIG_SYS_LIME_BASE; 339 } 340 341 #define W83782D_REG_CFG 0x40 342 #define W83782D_REG_BANK_SEL 0x4e 343 #define W83782D_REG_ADCCLK 0x4b 344 #define W83782D_REG_BEEP_CTRL 0x4d 345 #define W83782D_REG_BEEP_CTRL2 0x57 346 #define W83782D_REG_PWMOUT1 0x5b 347 #define W83782D_REG_VBAT 0x5d 348 349 static int w83782d_hwmon_init(void) 350 { 351 u8 buf; 352 353 if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) 354 return -1; 355 356 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); 357 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); 358 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); 359 360 buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); 361 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, 362 buf | 0x80); 363 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); 364 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); 365 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); 366 367 buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); 368 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 369 (buf & 0xf4) | 0x01); 370 return 0; 371 } 372 373 static void board_backlight_brightness(int br) 374 { 375 u32 reg; 376 u8 buf; 377 u8 old_buf; 378 379 /* Select bank 0 */ 380 if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) 381 goto err; 382 else 383 buf = old_buf & 0xf8; 384 385 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) 386 goto err; 387 388 if (br > 0) { 389 /* PWMOUT1 duty cycle ctrl */ 390 buf = 255 / (100 / br); 391 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) 392 goto err; 393 394 /* LEDs on */ 395 reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); 396 if (!(reg & BACKLIGHT_ENABLE)); 397 out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), 398 reg | BACKLIGHT_ENABLE); 399 } else { 400 buf = 0; 401 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) 402 goto err; 403 404 /* LEDs off */ 405 reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); 406 reg &= ~BACKLIGHT_ENABLE; 407 out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); 408 } 409 /* Restore previous bank setting */ 410 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) 411 goto err; 412 413 return; 414 err: 415 printf("W83782G I2C access failed\n"); 416 } 417 418 void board_backlight_switch (int flag) 419 { 420 char * param; 421 int rc; 422 423 if (w83782d_hwmon_init()) 424 printf ("hwmon IC init failed\n"); 425 426 if (flag) { 427 param = getenv("brightness"); 428 rc = param ? simple_strtol(param, NULL, 10) : -1; 429 if (rc < 0) 430 rc = DEFAULT_BRIGHTNESS; 431 } else { 432 rc = 0; 433 } 434 board_backlight_brightness(rc); 435 } 436 437 #if defined(CONFIG_CONSOLE_EXTRA_INFO) 438 /* 439 * Return text to be printed besides the logo. 440 */ 441 void video_get_info_str (int line_number, char *info) 442 { 443 if (line_number == 1) { 444 strcpy (info, " Board: Socrates"); 445 } else { 446 info [0] = '\0'; 447 } 448 } 449 #endif 450