1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Copyright 2004 Freescale Semiconductor. 6 * (C) Copyright 2002,2003, Motorola Inc. 7 * Xianghua Xiao, (X.Xiao@motorola.com) 8 * 9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <pci.h> 16 #include <asm/processor.h> 17 #include <asm/immap_85xx.h> 18 #include <ioports.h> 19 #include <flash.h> 20 #include <linux/libfdt.h> 21 #include <fdt_support.h> 22 #include <asm/io.h> 23 #include <i2c.h> 24 #include <mb862xx.h> 25 #include <video_fb.h> 26 #include "upm_table.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 extern flash_info_t flash_info[]; /* FLASH chips info */ 31 extern GraphicDevice mb862xx; 32 33 void local_bus_init (void); 34 ulong flash_get_size (ulong base, int banknum); 35 36 int checkboard (void) 37 { 38 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 39 char buf[64]; 40 int f; 41 int i = env_get_f("serial#", buf, sizeof(buf)); 42 #ifdef CONFIG_PCI 43 char *src; 44 #endif 45 46 puts("Board: Socrates"); 47 if (i > 0) { 48 puts(", serial# "); 49 puts(buf); 50 } 51 putc('\n'); 52 53 #ifdef CONFIG_PCI 54 /* Check the PCI_clk sel bit */ 55 if (in_be32(&gur->porpllsr) & (1<<15)) { 56 src = "SYSCLK"; 57 f = CONFIG_SYS_CLK_FREQ; 58 } else { 59 src = "PCI_CLK"; 60 f = CONFIG_PCI_CLK_FREQ; 61 } 62 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); 63 #else 64 printf ("PCI1: disabled\n"); 65 #endif 66 67 /* 68 * Initialize local bus. 69 */ 70 local_bus_init (); 71 return 0; 72 } 73 74 int misc_init_r (void) 75 { 76 /* 77 * Adjust flash start and offset to detected values 78 */ 79 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; 80 gd->bd->bi_flashoffset = 0; 81 82 /* 83 * Check if boot FLASH isn't max size 84 */ 85 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { 86 set_lbc_or(0, gd->bd->bi_flashstart | 87 (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); 88 set_lbc_br(0, gd->bd->bi_flashstart | 89 (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); 90 91 /* 92 * Re-check to get correct base address 93 */ 94 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); 95 } 96 97 /* 98 * Check if only one FLASH bank is available 99 */ 100 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { 101 set_lbc_or(1, 0); 102 set_lbc_br(1, 0); 103 104 /* 105 * Re-do flash protection upon new addresses 106 */ 107 flash_protect (FLAG_PROTECT_CLEAR, 108 gd->bd->bi_flashstart, 0xffffffff, 109 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); 110 111 /* Monitor protection ON by default */ 112 flash_protect (FLAG_PROTECT_SET, 113 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, 114 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); 115 116 /* Environment protection ON by default */ 117 flash_protect (FLAG_PROTECT_SET, 118 CONFIG_ENV_ADDR, 119 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, 120 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); 121 122 /* Redundant environment protection ON by default */ 123 flash_protect (FLAG_PROTECT_SET, 124 CONFIG_ENV_ADDR_REDUND, 125 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, 126 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); 127 } 128 129 return 0; 130 } 131 132 /* 133 * Initialize Local Bus 134 */ 135 void local_bus_init (void) 136 { 137 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 138 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 139 sys_info_t sysinfo; 140 uint clkdiv; 141 uint lbc_mhz; 142 uint lcrr = CONFIG_SYS_LBC_LCRR; 143 144 get_sys_info (&sysinfo); 145 clkdiv = lbc->lcrr & LCRR_CLKDIV; 146 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv; 147 148 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ 149 if (lbc_mhz >= 66) 150 lcrr &= ~LCRR_DBYP; /* DLL Enabled */ 151 else 152 lcrr |= LCRR_DBYP; /* DLL Bypass */ 153 154 out_be32 (&lbc->lcrr, lcrr); 155 asm ("sync;isync;msync"); 156 157 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ 158 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ 159 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ 160 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ 161 162 /* Init UPMA for FPGA access */ 163 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ 164 upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); 165 166 /* Init UPMB for Lime controller access */ 167 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ 168 upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); 169 } 170 171 #if defined(CONFIG_PCI) 172 /* 173 * Initialize PCI Devices, report devices found. 174 */ 175 176 #ifndef CONFIG_PCI_PNP 177 static struct pci_config_table pci_mpc85xxads_config_table[] = { 178 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 179 PCI_IDSEL_NUMBER, PCI_ANY_ID, 180 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 181 PCI_ENET0_MEMADDR, 182 PCI_COMMAND_MEMORY | 183 PCI_COMMAND_MASTER}}, 184 {} 185 }; 186 #endif 187 188 189 static struct pci_controller hose = { 190 #ifndef CONFIG_PCI_PNP 191 config_table:pci_mpc85xxads_config_table, 192 #endif 193 }; 194 195 #endif /* CONFIG_PCI */ 196 197 198 void pci_init_board (void) 199 { 200 #ifdef CONFIG_PCI 201 pci_mpc85xx_init (&hose); 202 #endif /* CONFIG_PCI */ 203 } 204 205 #ifdef CONFIG_BOARD_EARLY_INIT_R 206 int board_early_init_r (void) 207 { 208 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 209 210 /* set and reset the GPIO pin 2 which will reset the W83782G chip */ 211 out_8((unsigned char*)&gur->gpoutdr, 0x3F ); 212 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ 213 udelay(200); 214 out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); 215 216 return (0); 217 } 218 #endif /* CONFIG_BOARD_EARLY_INIT_R */ 219 220 #ifdef CONFIG_OF_BOARD_SETUP 221 int ft_board_setup(void *blob, bd_t *bd) 222 { 223 u32 val[12]; 224 int rc, i = 0; 225 226 ft_cpu_setup(blob, bd); 227 228 /* Fixup NOR FLASH mapping */ 229 val[i++] = 0; /* chip select number */ 230 val[i++] = 0; /* always 0 */ 231 val[i++] = gd->bd->bi_flashstart; 232 val[i++] = gd->bd->bi_flashsize; 233 234 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { 235 /* Fixup LIME mapping */ 236 val[i++] = 2; /* chip select number */ 237 val[i++] = 0; /* always 0 */ 238 val[i++] = CONFIG_SYS_LIME_BASE; 239 val[i++] = CONFIG_SYS_LIME_SIZE; 240 } 241 242 /* Fixup FPGA mapping */ 243 val[i++] = 3; /* chip select number */ 244 val[i++] = 0; /* always 0 */ 245 val[i++] = CONFIG_SYS_FPGA_BASE; 246 val[i++] = CONFIG_SYS_FPGA_SIZE; 247 248 rc = fdt_find_and_setprop(blob, "/localbus", "ranges", 249 val, i * sizeof(u32), 1); 250 if (rc) 251 printf("Unable to update localbus ranges, err=%s\n", 252 fdt_strerror(rc)); 253 254 return 0; 255 } 256 #endif /* CONFIG_OF_BOARD_SETUP */ 257 258 #define DEFAULT_BRIGHTNESS 25 259 #define BACKLIGHT_ENABLE (1 << 31) 260 261 static const gdc_regs init_regs [] = 262 { 263 {0x0100, 0x00010f00}, 264 {0x0020, 0x801901df}, 265 {0x0024, 0x00000000}, 266 {0x0028, 0x00000000}, 267 {0x002c, 0x00000000}, 268 {0x0110, 0x00000000}, 269 {0x0114, 0x00000000}, 270 {0x0118, 0x01df0320}, 271 {0x0004, 0x041f0000}, 272 {0x0008, 0x031f031f}, 273 {0x000c, 0x017f0349}, 274 {0x0010, 0x020c0000}, 275 {0x0014, 0x01df01e9}, 276 {0x0018, 0x00000000}, 277 {0x001c, 0x01e00320}, 278 {0x0100, 0x80010f00}, 279 {0x0, 0x0} 280 }; 281 282 const gdc_regs *board_get_regs (void) 283 { 284 return init_regs; 285 } 286 287 int lime_probe(void) 288 { 289 uint cfg_br2; 290 uint cfg_or2; 291 int type; 292 293 cfg_br2 = get_lbc_br(2); 294 cfg_or2 = get_lbc_or(2); 295 296 /* Configure GPCM for CS2 */ 297 set_lbc_br(2, 0); 298 set_lbc_or(2, 0xfc000410); 299 set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901); 300 301 /* Get controller type */ 302 type = mb862xx_probe(CONFIG_SYS_LIME_BASE); 303 304 /* Restore previous CS2 configuration */ 305 set_lbc_br(2, 0); 306 set_lbc_or(2, cfg_or2); 307 set_lbc_br(2, cfg_br2); 308 309 return (type == MB862XX_TYPE_LIME) ? 1 : 0; 310 } 311 312 /* Returns Lime base address */ 313 unsigned int board_video_init (void) 314 { 315 if (!lime_probe()) 316 return 0; 317 318 mb862xx.winSizeX = 800; 319 mb862xx.winSizeY = 480; 320 mb862xx.gdfIndex = GDF_15BIT_555RGB; 321 mb862xx.gdfBytesPP = 2; 322 323 return CONFIG_SYS_LIME_BASE; 324 } 325 326 #define W83782D_REG_CFG 0x40 327 #define W83782D_REG_BANK_SEL 0x4e 328 #define W83782D_REG_ADCCLK 0x4b 329 #define W83782D_REG_BEEP_CTRL 0x4d 330 #define W83782D_REG_BEEP_CTRL2 0x57 331 #define W83782D_REG_PWMOUT1 0x5b 332 #define W83782D_REG_VBAT 0x5d 333 334 static int w83782d_hwmon_init(void) 335 { 336 u8 buf; 337 338 if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) 339 return -1; 340 341 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); 342 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); 343 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); 344 345 buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); 346 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, 347 buf | 0x80); 348 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); 349 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); 350 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); 351 352 buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); 353 i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 354 (buf & 0xf4) | 0x01); 355 return 0; 356 } 357 358 static void board_backlight_brightness(int br) 359 { 360 u32 reg; 361 u8 buf; 362 u8 old_buf; 363 364 /* Select bank 0 */ 365 if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) 366 goto err; 367 else 368 buf = old_buf & 0xf8; 369 370 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) 371 goto err; 372 373 if (br > 0) { 374 /* PWMOUT1 duty cycle ctrl */ 375 buf = 255 / (100 / br); 376 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) 377 goto err; 378 379 /* LEDs on */ 380 reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); 381 if (!(reg & BACKLIGHT_ENABLE)) 382 out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), 383 reg | BACKLIGHT_ENABLE); 384 } else { 385 buf = 0; 386 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) 387 goto err; 388 389 /* LEDs off */ 390 reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); 391 reg &= ~BACKLIGHT_ENABLE; 392 out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); 393 } 394 /* Restore previous bank setting */ 395 if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) 396 goto err; 397 398 return; 399 err: 400 printf("W83782G I2C access failed\n"); 401 } 402 403 void board_backlight_switch (int flag) 404 { 405 char * param; 406 int rc; 407 408 if (w83782d_hwmon_init()) 409 printf ("hwmon IC init failed\n"); 410 411 if (flag) { 412 param = env_get("brightness"); 413 rc = param ? simple_strtol(param, NULL, 10) : -1; 414 if (rc < 0) 415 rc = DEFAULT_BRIGHTNESS; 416 } else { 417 rc = 0; 418 } 419 board_backlight_brightness(rc); 420 } 421 422 #if defined(CONFIG_CONSOLE_EXTRA_INFO) 423 /* 424 * Return text to be printed besides the logo. 425 */ 426 void video_get_info_str (int line_number, char *info) 427 { 428 if (line_number == 1) { 429 strcpy (info, " Board: Socrates"); 430 } else { 431 info [0] = '\0'; 432 } 433 } 434 #endif 435