1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 25 #include <common.h> 26 #include <asm/processor.h> 27 #include <asm/immap_85xx.h> 28 #include <asm/processor.h> 29 #include <asm/mmu.h> 30 #include <spd_sdram.h> 31 32 33 #if !defined(CONFIG_SPD_EEPROM) 34 /* 35 * Autodetect onboard DDR SDRAM on 85xx platforms 36 * 37 * NOTE: Some of the hardcoded values are hardware dependant, 38 * so this should be extended for other future boards 39 * using this routine! 40 */ 41 long int sdram_setup(int casl) 42 { 43 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); 44 45 /* 46 * Disable memory controller. 47 */ 48 ddr->cs0_config = 0; 49 ddr->sdram_cfg = 0; 50 51 ddr->cs0_bnds = CFG_DDR_CS0_BNDS; 52 ddr->cs0_config = CFG_DDR_CS0_CONFIG; 53 ddr->timing_cfg_0 = CFG_DDR_TIMING_0; 54 ddr->timing_cfg_1 = CFG_DDR_TIMING_1; 55 ddr->timing_cfg_2 = CFG_DDR_TIMING_2; 56 ddr->sdram_mode = CFG_DDR_MODE; 57 ddr->sdram_interval = CFG_DDR_INTERVAL; 58 ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2; 59 ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL; 60 61 asm ("sync;isync;msync"); 62 udelay(1000); 63 64 ddr->sdram_cfg = CFG_DDR_CONFIG; 65 asm ("sync; isync; msync"); 66 udelay(1000); 67 68 if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) { 69 /* 70 * OK, size detected -> all done 71 */ 72 return CFG_SDRAM_SIZE<<20; 73 } 74 75 return 0; /* nothing found ! */ 76 } 77 #endif 78 79 phys_size_t initdram (int board_type) 80 { 81 long dram_size = 0; 82 #if defined(CONFIG_SPD_EEPROM) 83 dram_size = spd_sdram (); 84 #else 85 dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); 86 #endif 87 return dram_size; 88 } 89 90 #if defined(CFG_DRAM_TEST) 91 int testdram (void) 92 { 93 uint *pstart = (uint *) CFG_MEMTEST_START; 94 uint *pend = (uint *) CFG_MEMTEST_END; 95 uint *p; 96 97 printf ("SDRAM test phase 1:\n"); 98 for (p = pstart; p < pend; p++) 99 *p = 0xaaaaaaaa; 100 101 for (p = pstart; p < pend; p++) { 102 if (*p != 0xaaaaaaaa) { 103 printf ("SDRAM test fails at: %08x\n", (uint) p); 104 return 1; 105 } 106 } 107 108 printf ("SDRAM test phase 2:\n"); 109 for (p = pstart; p < pend; p++) 110 *p = 0x55555555; 111 112 for (p = pstart; p < pend; p++) { 113 if (*p != 0x55555555) { 114 printf ("SDRAM test fails at: %08x\n", (uint) p); 115 return 1; 116 } 117 } 118 119 printf ("SDRAM test passed.\n"); 120 return 0; 121 } 122 #endif 123