1 /* 2 * Copyright (C) 2016 Stefano Babic <sbabic@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/iomux.h> 10 #include <asm/arch/mx6-pins.h> 11 #include <linux/errno.h> 12 #include <asm/gpio.h> 13 #include <asm/mach-imx/iomux-v3.h> 14 #include <asm/mach-imx/video.h> 15 #include <mmc.h> 16 #include <fsl_esdhc.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/io.h> 19 #include <asm/arch/sys_proto.h> 20 #include <spl.h> 21 #include <netdev.h> 22 #include <miiphy.h> 23 #include <micrel.h> 24 25 #include <common.h> 26 #include <malloc.h> 27 #include <fuse.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 32 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 33 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 35 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 36 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 41 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 42 43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 44 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 45 46 static iomux_v3_cfg_t const uart1_pads[] = { 47 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 48 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 49 }; 50 51 static iomux_v3_cfg_t const gpios_pads[] = { 52 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 53 }; 54 55 static iomux_v3_cfg_t const usdhc2_pads[] = { 56 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 57 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 58 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 59 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 60 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 61 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 62 IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ 63 }; 64 65 static iomux_v3_cfg_t const enet_pads[] = { 66 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 67 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 68 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 69 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 70 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 71 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 72 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 73 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 74 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 75 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 76 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 77 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 78 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 79 MUX_PAD_CTRL(ENET_PAD_CTRL)), 80 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 81 MUX_PAD_CTRL(ENET_PAD_CTRL)), 82 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 83 MUX_PAD_CTRL(ENET_PAD_CTRL)), 84 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), 85 }; 86 87 iomux_v3_cfg_t const enet_pads1[] = { 88 /* pin 35 - 1 (PHY_AD2) on reset */ 89 IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), 90 /* pin 32 - 1 - (MODE0) all */ 91 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), 92 /* pin 31 - 1 - (MODE1) all */ 93 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), 94 /* pin 28 - 1 - (MODE2) all */ 95 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 96 /* pin 27 - 1 - (MODE3) all */ 97 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 98 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 99 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), 100 /* pin 42 PHY nRST */ 101 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), 102 }; 103 104 static int mx6_rgmii_rework(struct phy_device *phydev) 105 { 106 107 /* min rx data delay */ 108 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 109 0x0); 110 /* min tx data delay */ 111 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 112 0x0); 113 /* max rx/tx clock delay, min rx/tx control */ 114 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 115 0xf0f0); 116 117 return 0; 118 } 119 120 int board_phy_config(struct phy_device *phydev) 121 { 122 mx6_rgmii_rework(phydev); 123 124 if (phydev->drv->config) 125 return phydev->drv->config(phydev); 126 127 return 0; 128 } 129 130 #define ENET_NRST IMX_GPIO_NR(1, 25) 131 132 void setup_iomux_enet(void) 133 { 134 SETUP_IOMUX_PADS(enet_pads); 135 136 } 137 138 int board_eth_init(bd_t *bis) 139 { 140 uint32_t base = IMX_FEC_BASE; 141 struct mii_dev *bus = NULL; 142 struct phy_device *phydev = NULL; 143 int ret; 144 145 setup_iomux_enet(); 146 147 bus = fec_get_miibus(base, -1); 148 if (!bus) 149 return -EINVAL; 150 /* scan phy */ 151 phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR), 152 PHY_INTERFACE_MODE_RGMII); 153 154 if (!phydev) { 155 ret = -EINVAL; 156 goto free_bus; 157 } 158 ret = fec_probe(bis, -1, base, bus, phydev); 159 if (ret) 160 goto free_phydev; 161 162 return 0; 163 164 free_phydev: 165 free(phydev); 166 free_bus: 167 free(bus); 168 return ret; 169 } 170 171 int board_early_init_f(void) 172 { 173 SETUP_IOMUX_PADS(uart1_pads); 174 175 return 0; 176 } 177 178 int board_init(void) 179 { 180 /* Address of boot parameters */ 181 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 182 183 /* Take in reset the ATMega processor */ 184 SETUP_IOMUX_PADS(gpios_pads); 185 gpio_direction_output(IMX_GPIO_NR(5, 4), 0); 186 187 return 0; 188 } 189 190 int dram_init(void) 191 { 192 gd->ram_size = imx_ddr_size(); 193 194 return 0; 195 } 196 197 struct fsl_esdhc_cfg usdhc_cfg[1] = { 198 {USDHC2_BASE_ADDR, 0}, 199 }; 200 201 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0) 202 int board_mmc_getcd(struct mmc *mmc) 203 { 204 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 205 int ret = 0; 206 207 if (cfg->esdhc_base == USDHC2_BASE_ADDR) 208 ret = 1; 209 210 return ret; 211 } 212 213 int board_mmc_init(bd_t *bis) 214 { 215 int ret; 216 217 SETUP_IOMUX_PADS(usdhc2_pads); 218 gpio_direction_input(USDHC2_CD_GPIO); 219 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 220 usdhc_cfg[0].max_bus_width = 4; 221 222 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 223 if (ret) { 224 printf("Warning: failed to initialize mmc dev \n"); 225 return ret; 226 } 227 228 return 0; 229 } 230 231 #if defined(CONFIG_SPL_BUILD) 232 #include <asm/arch/mx6-ddr.h> 233 234 /* 235 * Driving strength: 236 * 0x30 == 40 Ohm 237 * 0x28 == 48 Ohm 238 */ 239 #define IMX6SDL_DRIVE_STRENGTH 0x230 240 241 242 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 243 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 244 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 245 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 246 .dram_cas = IMX6SDL_DRIVE_STRENGTH, 247 .dram_ras = IMX6SDL_DRIVE_STRENGTH, 248 .dram_reset = IMX6SDL_DRIVE_STRENGTH, 249 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 250 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 251 .dram_sdba2 = 0x00000000, 252 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 253 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 254 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 255 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 256 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 257 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 258 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 259 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 260 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 261 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 262 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 263 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 264 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 265 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 266 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 267 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 268 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 269 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 270 }; 271 272 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 273 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 274 .grp_ddr_type = 0x000c0000, 275 .grp_ddrmode_ctl = 0x00020000, 276 .grp_ddrpke = 0x00000000, 277 .grp_addds = IMX6SDL_DRIVE_STRENGTH, 278 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 279 .grp_ddrmode = 0x00020000, 280 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 281 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 282 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 283 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 284 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 285 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 286 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 287 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 288 }; 289 290 /* MT41K128M16JT-125 */ 291 static struct mx6_ddr3_cfg mt41k128m16jt_125 = { 292 /* quad = 1066, duallite = 800 */ 293 .mem_speed = 1066, 294 .density = 2, 295 .width = 16, 296 .banks = 8, 297 .rowaddr = 14, 298 .coladdr = 10, 299 .pagesz = 2, 300 .trcd = 1375, 301 .trcmin = 4875, 302 .trasmin = 3500, 303 .SRT = 0, 304 }; 305 306 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { 307 .p0_mpwldectrl0 = 0x0043004E, 308 .p0_mpwldectrl1 = 0x003D003F, 309 .p1_mpwldectrl0 = 0x00230021, 310 .p1_mpwldectrl1 = 0x0028003E, 311 .p0_mpdgctrl0 = 0x42580250, 312 .p0_mpdgctrl1 = 0x0238023C, 313 .p1_mpdgctrl0 = 0x422C0238, 314 .p1_mpdgctrl1 = 0x02180228, 315 .p0_mprddlctl = 0x44464A46, 316 .p1_mprddlctl = 0x44464A42, 317 .p0_mpwrdlctl = 0x36343236, 318 .p1_mpwrdlctl = 0x36343230, 319 }; 320 321 /* DDR 64bit 1GB */ 322 static struct mx6_ddr_sysinfo mem_qdl = { 323 .dsize = 2, 324 .cs1_mirror = 0, 325 /* config for full 4GB range so that get_mem_size() works */ 326 .cs_density = 32, 327 .ncs = 1, 328 .bi_on = 1, 329 .rtt_nom = 1, 330 .rtt_wr = 1, 331 .ralat = 5, 332 .walat = 0, 333 .mif3_mode = 3, 334 .rst_to_cke = 0x23, 335 .sde_to_rst = 0x10, 336 .refsel = 1, /* Refresh cycles at 32KHz */ 337 .refr = 7, /* 8 refresh commands per refresh cycle */ 338 }; 339 340 static void ccgr_init(void) 341 { 342 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 343 344 /* set the default clock gate to save power */ 345 writel(0x00C03F3F, &ccm->CCGR0); 346 writel(0x0030FC03, &ccm->CCGR1); 347 writel(0x0FFFC000, &ccm->CCGR2); 348 writel(0x3FF00000, &ccm->CCGR3); 349 writel(0x00FFF300, &ccm->CCGR4); 350 writel(0xFFFFFFFF, &ccm->CCGR5); 351 writel(0x000003FF, &ccm->CCGR6); 352 } 353 354 static void spl_dram_init(void) 355 { 356 if (is_cpu_type(MXC_CPU_MX6DL)) { 357 mt41k128m16jt_125.mem_speed = 800; 358 mem_qdl.rtt_nom = 1; 359 mem_qdl.rtt_wr = 1; 360 361 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 362 mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125); 363 } else { 364 printf("Wrong CPU for this board\n"); 365 return; 366 } 367 368 udelay(100); 369 370 #ifdef CONFIG_MX6_DDRCAL 371 372 /* Perform DDR DRAM calibration */ 373 mmdc_do_write_level_calibration(&mem_qdl); 374 mmdc_do_dqs_calibration(&mem_qdl); 375 #endif 376 } 377 378 static void check_bootcfg(void) 379 { 380 u32 val5, val6; 381 382 fuse_sense(0, 5, &val5); 383 fuse_sense(0, 6, &val6); 384 /* Check if boot from MMC */ 385 if (val6 & 0x10) { 386 puts("BT_FUSE_SEL already fused, will do nothing\n"); 387 return; 388 } 389 fuse_prog(0, 5, 0x00000840); 390 /* BT_FUSE_SEL */ 391 fuse_prog(0, 6, 0x00000010); 392 393 do_reset(NULL, 0, 0, NULL); 394 } 395 396 void board_init_f(ulong dummy) 397 { 398 ccgr_init(); 399 400 /* setup AIPS and disable watchdog */ 401 arch_cpu_init(); 402 403 gpr_init(); 404 405 /* iomux */ 406 board_early_init_f(); 407 408 /* setup GP timer */ 409 timer_init(); 410 411 /* UART clocks enabled and gd valid - init serial console */ 412 preloader_console_init(); 413 414 /* DDR initialization */ 415 spl_dram_init(); 416 417 /* Set fuses for new boards and reboot if not set */ 418 check_bootcfg(); 419 420 /* Clear the BSS. */ 421 memset(__bss_start, 0, __bss_end - __bss_start); 422 423 /* load/boot image from boot device */ 424 board_init_r(NULL, 0); 425 } 426 #endif 427