1 /* 2 * mux.c 3 * 4 * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/mux.h> 13 #include <asm/io.h> 14 #include "board.h" 15 16 /* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */ 17 static struct module_pin_mux uart0_pin_mux[] = { 18 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 19 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 20 {-1}, 21 }; 22 23 /* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */ 24 25 /* I2C pins C16(scl)/C17(sda) */ 26 static struct module_pin_mux i2c0_pin_mux[] = { 27 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 28 PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */ 29 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 30 PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */ 31 {-1}, 32 }; 33 34 /* MMC0 pins */ 35 static struct module_pin_mux mmc0_pin_mux[] = { 36 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 37 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 38 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 39 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 40 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 41 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 42 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 43 {-1}, 44 }; 45 46 /* MII pins */ 47 static struct module_pin_mux mii1_pin_mux[] = { 48 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ 49 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ 50 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ 51 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ 52 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ 53 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ 54 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ 55 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ 56 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ 57 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ 58 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ 59 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ 60 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ 61 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 62 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 63 {-1}, 64 }; 65 66 /* NAND pins */ 67 static struct module_pin_mux nand_pin_mux[] = { 68 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 69 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 70 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 71 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 72 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 73 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 74 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 75 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 76 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 77 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 78 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 79 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 80 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 81 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 82 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 83 {-1}, 84 }; 85 86 void enable_uart0_pin_mux(void) 87 { 88 configure_module_pin_mux(uart0_pin_mux); 89 } 90 91 void enable_board_pin_mux() 92 { 93 configure_module_pin_mux(i2c0_pin_mux); 94 configure_module_pin_mux(uart0_pin_mux); 95 configure_module_pin_mux(mii1_pin_mux); 96 configure_module_pin_mux(mmc0_pin_mux); 97 configure_module_pin_mux(nand_pin_mux); 98 } 99