1 /* 2 * Board functions for Siemens TAURUS (AT91SAM9G20) based boards 3 * (C) Copyright Siemens AG 4 * 5 * Based on: 6 * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c 7 * 8 * (C) Copyright 2007-2008 9 * Stelian Pop <stelian@popies.net> 10 * Lead Tech Design <www.leadtechdesign.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <command.h> 16 #include <common.h> 17 #include <asm/io.h> 18 #include <asm/arch/at91sam9260_matrix.h> 19 #include <asm/arch/at91sam9_smc.h> 20 #include <asm/arch/at91_common.h> 21 #include <asm/arch/at91_pmc.h> 22 #include <asm/arch/at91_rstc.h> 23 #include <asm/arch/gpio.h> 24 #include <asm/arch/at91sam9_sdramc.h> 25 #include <asm/arch/clk.h> 26 #include <linux/mtd/nand.h> 27 #include <atmel_mci.h> 28 #include <asm/arch/at91_spi.h> 29 #include <spi.h> 30 31 #include <net.h> 32 #include <netdev.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static void taurus_nand_hw_init(void) 37 { 38 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 39 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 40 unsigned long csa; 41 42 /* Assign CS3 to NAND/SmartMedia Interface */ 43 csa = readl(&matrix->ebicsa); 44 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 45 writel(csa, &matrix->ebicsa); 46 47 /* Configure SMC CS3 for NAND/SmartMedia */ 48 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 49 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 50 &smc->cs[3].setup); 51 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | 52 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3), 53 &smc->cs[3].pulse); 54 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 55 &smc->cs[3].cycle); 56 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 57 AT91_SMC_MODE_EXNW_DISABLE | 58 AT91_SMC_MODE_DBW_8 | 59 AT91_SMC_MODE_TDF_CYCLE(3), 60 &smc->cs[3].mode); 61 62 /* Configure RDY/BSY */ 63 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 64 65 /* Enable NandFlash */ 66 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 67 } 68 69 #if defined(CONFIG_SPL_BUILD) 70 #include <spl.h> 71 #include <nand.h> 72 #include <spi_flash.h> 73 74 void matrix_init(void) 75 { 76 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; 77 78 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) 79 | AT91_MATRIX_SLOT_CYCLE_(0x40), 80 &mat->scfg[3]); 81 } 82 83 #if defined(CONFIG_BOARD_AXM) 84 static int at91_is_recovery(void) 85 { 86 if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) && 87 (at91_get_gpio_value(AT91_PIN_PA27) == 0)) 88 return 1; 89 90 return 0; 91 } 92 #elif defined(CONFIG_BOARD_TAURUS) 93 static int at91_is_recovery(void) 94 { 95 if (at91_get_gpio_value(AT91_PIN_PA31) == 0) 96 return 1; 97 98 return 0; 99 } 100 #endif 101 102 void spl_board_init(void) 103 { 104 taurus_nand_hw_init(); 105 at91_spi0_hw_init(TAURUS_SPI_MASK); 106 107 #if defined(CONFIG_BOARD_AXM) 108 /* Configure LED PINs */ 109 at91_set_gpio_output(AT91_PIN_PA6, 0); 110 at91_set_gpio_output(AT91_PIN_PA8, 0); 111 at91_set_gpio_output(AT91_PIN_PA9, 0); 112 at91_set_gpio_output(AT91_PIN_PA10, 0); 113 at91_set_gpio_output(AT91_PIN_PA11, 0); 114 at91_set_gpio_output(AT91_PIN_PA12, 0); 115 116 /* Configure recovery button PINs */ 117 at91_set_gpio_input(AT91_PIN_PA26, 1); 118 at91_set_gpio_input(AT91_PIN_PA27, 1); 119 #elif defined(CONFIG_BOARD_TAURUS) 120 at91_set_gpio_input(AT91_PIN_PA31, 1); 121 #endif 122 123 /* check for recovery mode */ 124 if (at91_is_recovery() == 1) { 125 struct spi_flash *flash; 126 127 puts("Recovery button pressed\n"); 128 nand_init(); 129 spl_nand_erase_one(0, 0); 130 flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, 131 0, 132 CONFIG_SF_DEFAULT_SPEED, 133 CONFIG_SF_DEFAULT_MODE); 134 if (!flash) { 135 puts("no flash\n"); 136 } else { 137 puts("erase spi flash sector 0\n"); 138 spi_flash_erase(flash, 0, 139 CONFIG_SYS_NAND_U_BOOT_SIZE); 140 } 141 } 142 } 143 144 #define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \ 145 |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ 146 | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \ 147 | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \ 148 | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10)) 149 150 void sdramc_configure(unsigned int mask) 151 { 152 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; 153 struct sdramc_reg setting; 154 155 at91_sdram_hw_init(); 156 setting.cr = SDRAM_BASE_CONF | mask; 157 setting.mdr = AT91_SDRAMC_MD_SDRAM; 158 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; 159 160 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | 161 AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, 162 &ma->ebicsa); 163 164 sdramc_initialize(ATMEL_BASE_CS1, &setting); 165 } 166 167 void mem_init(void) 168 { 169 unsigned int ram_size = 0; 170 171 /* Configure SDRAM for 128MB */ 172 sdramc_configure(AT91_SDRAMC_NC_10); 173 174 /* Do memtest for 128MB */ 175 ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 176 CONFIG_SYS_SDRAM_SIZE); 177 178 /* 179 * If 32MB or 16MB should be supported check also for 180 * expected mirroring at A16 and A17 181 * To find mirror addresses depends how the collumns are connected 182 * at RAM (internaly or externaly) 183 * If the collumns are not in inverted order the mirror size effect 184 * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal 185 */ 186 187 /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/ 188 if (ram_size == 0x800) { 189 printf("\n\r 64MB"); 190 sdramc_configure(AT91_SDRAMC_NC_9); 191 } else { 192 /* Size already initialized */ 193 printf("\n\r 128MB"); 194 } 195 } 196 #endif 197 198 #ifdef CONFIG_MACB 199 static void siemens_phy_reset(void) 200 { 201 /* 202 * we need to reset PHY for 200us 203 * because of bug in ATMEL G20 CPU (undefined initial state of GPIO) 204 */ 205 if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) == 206 AT91_RSTC_RSTTYP_GENERAL) 207 at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */ 208 } 209 210 static void taurus_macb_hw_init(void) 211 { 212 /* Enable EMAC clock */ 213 at91_periph_clk_enable(ATMEL_ID_EMAC0); 214 215 /* 216 * Disable pull-up on: 217 * RXDV (PA17) => PHY normal mode (not Test mode) 218 * ERX0 (PA14) => PHY ADDR0 219 * ERX1 (PA15) => PHY ADDR1 220 * ERX2 (PA25) => PHY ADDR2 221 * ERX3 (PA26) => PHY ADDR3 222 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 223 * 224 * PHY has internal pull-down 225 */ 226 at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0); 227 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 228 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0); 229 at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0); 230 at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0); 231 at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0); 232 233 siemens_phy_reset(); 234 235 at91_phy_reset(); 236 237 at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */ 238 239 /* Re-enable pull-up */ 240 at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1); 241 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 242 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); 243 at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1); 244 at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1); 245 at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1); 246 247 /* Initialize EMAC=MACB hardware */ 248 at91_macb_hw_init(); 249 } 250 #endif 251 252 #ifdef CONFIG_GENERIC_ATMEL_MCI 253 int board_mmc_init(bd_t *bd) 254 { 255 at91_mci_hw_init(); 256 257 return atmel_mci_init((void *)ATMEL_BASE_MCI); 258 } 259 #endif 260 261 int board_early_init_f(void) 262 { 263 /* Enable clocks for all PIOs */ 264 at91_periph_clk_enable(ATMEL_ID_PIOA); 265 at91_periph_clk_enable(ATMEL_ID_PIOB); 266 at91_periph_clk_enable(ATMEL_ID_PIOC); 267 268 at91_seriald_hw_init(); 269 270 return 0; 271 } 272 273 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 274 { 275 return bus == 0 && cs == 0; 276 } 277 278 void spi_cs_activate(struct spi_slave *slave) 279 { 280 at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0); 281 } 282 283 void spi_cs_deactivate(struct spi_slave *slave) 284 { 285 at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); 286 } 287 288 #ifdef CONFIG_USB_GADGET_AT91 289 #include <linux/usb/at91_udc.h> 290 291 void at91_udp_hw_init(void) 292 { 293 at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; 294 295 /* Enable PLLB */ 296 writel(get_pllb_init(), &pmc->pllbr); 297 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) 298 ; 299 300 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ 301 at91_periph_clk_enable(ATMEL_ID_UDP); 302 303 writel(AT91SAM926x_PMC_UDP, &pmc->scer); 304 } 305 306 struct at91_udc_data board_udc_data = { 307 .baseaddr = ATMEL_BASE_UDP0, 308 }; 309 #endif 310 311 int board_init(void) 312 { 313 /* adress of boot parameters */ 314 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 315 316 #ifdef CONFIG_CMD_NAND 317 taurus_nand_hw_init(); 318 #endif 319 #ifdef CONFIG_MACB 320 taurus_macb_hw_init(); 321 #endif 322 at91_spi0_hw_init(TAURUS_SPI_MASK); 323 #ifdef CONFIG_USB_GADGET_AT91 324 at91_udp_hw_init(); 325 at91_udc_probe(&board_udc_data); 326 #endif 327 328 return 0; 329 } 330 331 int dram_init(void) 332 { 333 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 334 CONFIG_SYS_SDRAM_SIZE); 335 return 0; 336 } 337 338 int board_eth_init(bd_t *bis) 339 { 340 int rc = 0; 341 #ifdef CONFIG_MACB 342 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); 343 #endif 344 return rc; 345 } 346 347 #if !defined(CONFIG_SPL_BUILD) 348 #if defined(CONFIG_BOARD_AXM) 349 /* 350 * Booting the Fallback Image. 351 * 352 * The function is used to provide and 353 * boot the image with the fallback 354 * parameters, incase if the faulty image 355 * in upgraded over the base firmware. 356 * 357 */ 358 static int upgrade_failure_fallback(void) 359 { 360 char *partitionset_active = NULL; 361 char *rootfs = NULL; 362 char *rootfs_fallback = NULL; 363 char *kern_off; 364 char *kern_off_fb; 365 char *kern_size; 366 char *kern_size_fb; 367 368 partitionset_active = getenv("partitionset_active"); 369 if (partitionset_active) { 370 if (partitionset_active[0] == 'A') 371 setenv("partitionset_active", "B"); 372 else 373 setenv("partitionset_active", "A"); 374 } else { 375 printf("partitionset_active missing.\n"); 376 return -ENOENT; 377 } 378 379 rootfs = getenv("rootfs"); 380 rootfs_fallback = getenv("rootfs_fallback"); 381 setenv("rootfs", rootfs_fallback); 382 setenv("rootfs_fallback", rootfs); 383 384 kern_size = getenv("kernel_size"); 385 kern_size_fb = getenv("kernel_size_fallback"); 386 setenv("kernel_size", kern_size_fb); 387 setenv("kernel_size_fallback", kern_size); 388 389 kern_off = getenv("kernel_Off"); 390 kern_off_fb = getenv("kernel_Off_fallback"); 391 setenv("kernel_Off", kern_off_fb); 392 setenv("kernel_Off_fallback", kern_off); 393 394 setenv("bootargs", '\0'); 395 setenv("upgrade_available", '\0'); 396 setenv("boot_retries", '\0'); 397 saveenv(); 398 399 return 0; 400 } 401 402 static int do_upgrade_available(cmd_tbl_t *cmdtp, int flag, int argc, 403 char * const argv[]) 404 { 405 unsigned long upgrade_available = 0; 406 unsigned long boot_retry = 0; 407 char boot_buf[10]; 408 409 upgrade_available = simple_strtoul(getenv("upgrade_available"), NULL, 410 10); 411 if (upgrade_available) { 412 boot_retry = simple_strtoul(getenv("boot_retries"), NULL, 10); 413 boot_retry++; 414 sprintf(boot_buf, "%lx", boot_retry); 415 setenv("boot_retries", boot_buf); 416 saveenv(); 417 418 /* 419 * Here the boot_retries count is checked, and if the 420 * count becomes greater than 2 switch back to the 421 * fallback, and reset the board. 422 */ 423 424 if (boot_retry > 2) { 425 if (upgrade_failure_fallback() == 0) 426 do_reset(NULL, 0, 0, NULL); 427 return -1; 428 } 429 } 430 return 0; 431 } 432 433 U_BOOT_CMD( 434 upgrade_available, 1, 1, do_upgrade_available, 435 "check Siemens update", 436 "no parameters" 437 ); 438 #endif 439 #endif 440