1 /* 2 * Board functions for Siemens TAURUS (AT91SAM9G20) based boards 3 * (C) Copyright Siemens AG 4 * 5 * Based on: 6 * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c 7 * 8 * (C) Copyright 2007-2008 9 * Stelian Pop <stelian@popies.net> 10 * Lead Tech Design <www.leadtechdesign.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <command.h> 16 #include <common.h> 17 #include <asm/io.h> 18 #include <asm/arch/at91sam9260_matrix.h> 19 #include <asm/arch/at91sam9_smc.h> 20 #include <asm/arch/at91_common.h> 21 #include <asm/arch/at91_rstc.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/at91sam9_sdramc.h> 24 #include <asm/arch/clk.h> 25 #include <linux/mtd/nand.h> 26 #include <atmel_mci.h> 27 #include <asm/arch/at91_spi.h> 28 #include <spi.h> 29 30 #include <net.h> 31 #include <netdev.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 static void taurus_nand_hw_init(void) 36 { 37 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 38 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 39 unsigned long csa; 40 41 /* Assign CS3 to NAND/SmartMedia Interface */ 42 csa = readl(&matrix->ebicsa); 43 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 44 writel(csa, &matrix->ebicsa); 45 46 /* Configure SMC CS3 for NAND/SmartMedia */ 47 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 48 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 49 &smc->cs[3].setup); 50 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | 51 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3), 52 &smc->cs[3].pulse); 53 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 54 &smc->cs[3].cycle); 55 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 56 AT91_SMC_MODE_EXNW_DISABLE | 57 AT91_SMC_MODE_DBW_8 | 58 AT91_SMC_MODE_TDF_CYCLE(3), 59 &smc->cs[3].mode); 60 61 /* Configure RDY/BSY */ 62 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 63 64 /* Enable NandFlash */ 65 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 66 } 67 68 #if defined(CONFIG_SPL_BUILD) 69 #include <spl.h> 70 #include <nand.h> 71 #include <spi_flash.h> 72 73 void matrix_init(void) 74 { 75 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; 76 77 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) 78 | AT91_MATRIX_SLOT_CYCLE_(0x40), 79 &mat->scfg[3]); 80 } 81 82 #if defined(CONFIG_BOARD_AXM) 83 static int at91_is_recovery(void) 84 { 85 if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) && 86 (at91_get_gpio_value(AT91_PIN_PA27) == 0)) 87 return 1; 88 89 return 0; 90 } 91 #elif defined(CONFIG_BOARD_TAURUS) 92 static int at91_is_recovery(void) 93 { 94 if (at91_get_gpio_value(AT91_PIN_PA31) == 0) 95 return 1; 96 97 return 0; 98 } 99 #endif 100 101 void spl_board_init(void) 102 { 103 taurus_nand_hw_init(); 104 at91_spi0_hw_init(TAURUS_SPI_MASK); 105 106 #if defined(CONFIG_BOARD_AXM) 107 /* Configure LED PINs */ 108 at91_set_gpio_output(AT91_PIN_PA6, 0); 109 at91_set_gpio_output(AT91_PIN_PA8, 0); 110 at91_set_gpio_output(AT91_PIN_PA9, 0); 111 at91_set_gpio_output(AT91_PIN_PA10, 0); 112 at91_set_gpio_output(AT91_PIN_PA11, 0); 113 at91_set_gpio_output(AT91_PIN_PA12, 0); 114 115 /* Configure recovery button PINs */ 116 at91_set_gpio_input(AT91_PIN_PA26, 1); 117 at91_set_gpio_input(AT91_PIN_PA27, 1); 118 #elif defined(CONFIG_BOARD_TAURUS) 119 at91_set_gpio_input(AT91_PIN_PA31, 1); 120 #endif 121 122 /* check for recovery mode */ 123 if (at91_is_recovery() == 1) { 124 struct spi_flash *flash; 125 126 puts("Recovery button pressed\n"); 127 nand_init(); 128 spl_nand_erase_one(0, 0); 129 flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, 130 0, 131 CONFIG_SF_DEFAULT_SPEED, 132 CONFIG_SF_DEFAULT_MODE); 133 if (!flash) { 134 puts("no flash\n"); 135 } else { 136 puts("erase spi flash sector 0\n"); 137 spi_flash_erase(flash, 0, 138 CONFIG_SYS_NAND_U_BOOT_SIZE); 139 } 140 } 141 } 142 143 #define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \ 144 |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ 145 | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \ 146 | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \ 147 | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10)) 148 149 void sdramc_configure(unsigned int mask) 150 { 151 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; 152 struct sdramc_reg setting; 153 154 at91_sdram_hw_init(); 155 setting.cr = SDRAM_BASE_CONF | mask; 156 setting.mdr = AT91_SDRAMC_MD_SDRAM; 157 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; 158 159 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | 160 AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, 161 &ma->ebicsa); 162 163 sdramc_initialize(ATMEL_BASE_CS1, &setting); 164 } 165 166 void mem_init(void) 167 { 168 unsigned int ram_size = 0; 169 170 /* Configure SDRAM for 128MB */ 171 sdramc_configure(AT91_SDRAMC_NC_10); 172 173 /* Do memtest for 128MB */ 174 ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 175 CONFIG_SYS_SDRAM_SIZE); 176 177 /* 178 * If 32MB or 16MB should be supported check also for 179 * expected mirroring at A16 and A17 180 * To find mirror addresses depends how the collumns are connected 181 * at RAM (internaly or externaly) 182 * If the collumns are not in inverted order the mirror size effect 183 * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal 184 */ 185 186 /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/ 187 if (ram_size == 0x800) { 188 printf("\n\r 64MB"); 189 sdramc_configure(AT91_SDRAMC_NC_9); 190 } else { 191 /* Size already initialized */ 192 printf("\n\r 128MB"); 193 } 194 } 195 #endif 196 197 #ifdef CONFIG_MACB 198 static void siemens_phy_reset(void) 199 { 200 /* 201 * we need to reset PHY for 200us 202 * because of bug in ATMEL G20 CPU (undefined initial state of GPIO) 203 */ 204 if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) == 205 AT91_RSTC_RSTTYP_GENERAL) 206 at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */ 207 } 208 209 static void taurus_macb_hw_init(void) 210 { 211 /* Enable EMAC clock */ 212 at91_periph_clk_enable(ATMEL_ID_EMAC0); 213 214 /* 215 * Disable pull-up on: 216 * RXDV (PA17) => PHY normal mode (not Test mode) 217 * ERX0 (PA14) => PHY ADDR0 218 * ERX1 (PA15) => PHY ADDR1 219 * ERX2 (PA25) => PHY ADDR2 220 * ERX3 (PA26) => PHY ADDR3 221 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 222 * 223 * PHY has internal pull-down 224 */ 225 at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0); 226 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 227 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0); 228 at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0); 229 at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0); 230 at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0); 231 232 siemens_phy_reset(); 233 234 at91_phy_reset(); 235 236 at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */ 237 238 /* Re-enable pull-up */ 239 at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1); 240 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 241 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); 242 at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1); 243 at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1); 244 at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1); 245 246 /* Initialize EMAC=MACB hardware */ 247 at91_macb_hw_init(); 248 } 249 #endif 250 251 #ifdef CONFIG_GENERIC_ATMEL_MCI 252 int board_mmc_init(bd_t *bd) 253 { 254 at91_mci_hw_init(); 255 256 return atmel_mci_init((void *)ATMEL_BASE_MCI); 257 } 258 #endif 259 260 int board_early_init_f(void) 261 { 262 /* Enable clocks for all PIOs */ 263 at91_periph_clk_enable(ATMEL_ID_PIOA); 264 at91_periph_clk_enable(ATMEL_ID_PIOB); 265 at91_periph_clk_enable(ATMEL_ID_PIOC); 266 267 at91_seriald_hw_init(); 268 269 return 0; 270 } 271 272 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 273 { 274 return bus == 0 && cs == 0; 275 } 276 277 void spi_cs_activate(struct spi_slave *slave) 278 { 279 at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0); 280 } 281 282 void spi_cs_deactivate(struct spi_slave *slave) 283 { 284 at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); 285 } 286 287 #ifdef CONFIG_USB_GADGET_AT91 288 #include <linux/usb/at91_udc.h> 289 290 void at91_udp_hw_init(void) 291 { 292 /* Enable PLLB */ 293 at91_pllb_clk_enable(get_pllb_init()); 294 295 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ 296 at91_periph_clk_enable(ATMEL_ID_UDP); 297 298 at91_system_clk_enable(AT91SAM926x_PMC_UDP); 299 } 300 301 struct at91_udc_data board_udc_data = { 302 .baseaddr = ATMEL_BASE_UDP0, 303 }; 304 #endif 305 306 int board_init(void) 307 { 308 /* adress of boot parameters */ 309 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 310 311 #ifdef CONFIG_CMD_NAND 312 taurus_nand_hw_init(); 313 #endif 314 #ifdef CONFIG_MACB 315 taurus_macb_hw_init(); 316 #endif 317 at91_spi0_hw_init(TAURUS_SPI_MASK); 318 #ifdef CONFIG_USB_GADGET_AT91 319 at91_udp_hw_init(); 320 at91_udc_probe(&board_udc_data); 321 #endif 322 323 return 0; 324 } 325 326 int dram_init(void) 327 { 328 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 329 CONFIG_SYS_SDRAM_SIZE); 330 return 0; 331 } 332 333 int board_eth_init(bd_t *bis) 334 { 335 int rc = 0; 336 #ifdef CONFIG_MACB 337 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); 338 #endif 339 return rc; 340 } 341 342 #if !defined(CONFIG_SPL_BUILD) 343 #if defined(CONFIG_BOARD_AXM) 344 /* 345 * Booting the Fallback Image. 346 * 347 * The function is used to provide and 348 * boot the image with the fallback 349 * parameters, incase if the faulty image 350 * in upgraded over the base firmware. 351 * 352 */ 353 static int upgrade_failure_fallback(void) 354 { 355 char *partitionset_active = NULL; 356 char *rootfs = NULL; 357 char *rootfs_fallback = NULL; 358 char *kern_off; 359 char *kern_off_fb; 360 char *kern_size; 361 char *kern_size_fb; 362 363 partitionset_active = getenv("partitionset_active"); 364 if (partitionset_active) { 365 if (partitionset_active[0] == 'A') 366 setenv("partitionset_active", "B"); 367 else 368 setenv("partitionset_active", "A"); 369 } else { 370 printf("partitionset_active missing.\n"); 371 return -ENOENT; 372 } 373 374 rootfs = getenv("rootfs"); 375 rootfs_fallback = getenv("rootfs_fallback"); 376 setenv("rootfs", rootfs_fallback); 377 setenv("rootfs_fallback", rootfs); 378 379 kern_size = getenv("kernel_size"); 380 kern_size_fb = getenv("kernel_size_fallback"); 381 setenv("kernel_size", kern_size_fb); 382 setenv("kernel_size_fallback", kern_size); 383 384 kern_off = getenv("kernel_Off"); 385 kern_off_fb = getenv("kernel_Off_fallback"); 386 setenv("kernel_Off", kern_off_fb); 387 setenv("kernel_Off_fallback", kern_off); 388 389 setenv("bootargs", '\0'); 390 setenv("upgrade_available", '\0'); 391 setenv("boot_retries", '\0'); 392 saveenv(); 393 394 return 0; 395 } 396 397 static int do_upgrade_available(cmd_tbl_t *cmdtp, int flag, int argc, 398 char * const argv[]) 399 { 400 unsigned long upgrade_available = 0; 401 unsigned long boot_retry = 0; 402 char boot_buf[10]; 403 404 upgrade_available = simple_strtoul(getenv("upgrade_available"), NULL, 405 10); 406 if (upgrade_available) { 407 boot_retry = simple_strtoul(getenv("boot_retries"), NULL, 10); 408 boot_retry++; 409 sprintf(boot_buf, "%lx", boot_retry); 410 setenv("boot_retries", boot_buf); 411 saveenv(); 412 413 /* 414 * Here the boot_retries count is checked, and if the 415 * count becomes greater than 2 switch back to the 416 * fallback, and reset the board. 417 */ 418 419 if (boot_retry > 2) { 420 if (upgrade_failure_fallback() == 0) 421 do_reset(NULL, 0, 0, NULL); 422 return -1; 423 } 424 } 425 return 0; 426 } 427 428 U_BOOT_CMD( 429 upgrade_available, 1, 1, do_upgrade_available, 430 "check Siemens update", 431 "no parameters" 432 ); 433 #endif 434 #endif 435