1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Achim Ehrlich <aehrlich@taskit.de> 7 * taskit GmbH <www.taskit.de> 8 * 9 * (C) Copyright 2012- 10 * Markus Hubig <mhubig@imko.de> 11 * IMKO GmbH <www.imko.de> 12 * (C) Copyright 2014 13 * Heiko Schocher <hs@denx.de> 14 * DENX Software Engineering GmbH 15 * 16 * SPDX-License-Identifier: GPL-2.0+ 17 */ 18 19 #include <common.h> 20 #include <dm.h> 21 #include <asm/io.h> 22 #include <asm/arch/at91sam9_sdramc.h> 23 #include <asm/arch/at91sam9260_matrix.h> 24 #include <asm/arch/at91sam9_smc.h> 25 #include <asm/arch/at91_common.h> 26 #include <asm/arch/atmel_serial.h> 27 #include <asm/arch/at91_spi.h> 28 #include <spi.h> 29 #include <asm/arch/clk.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/gpio.h> 32 #include <watchdog.h> 33 # include <net.h> 34 #ifndef CONFIG_DM_ETH 35 # include <netdev.h> 36 #endif 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 static void smartweb_request_gpio(void) 41 { 42 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); 43 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); 44 gpio_request(AT91_PIN_PA26, "ena PHY"); 45 } 46 47 static void smartweb_nand_hw_init(void) 48 { 49 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 50 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 51 unsigned long csa; 52 53 /* Assign CS3 to NAND/SmartMedia Interface */ 54 csa = readl(&matrix->ebicsa); 55 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 56 writel(csa, &matrix->ebicsa); 57 58 /* Configure SMC CS3 for NAND/SmartMedia */ 59 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 60 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 61 &smc->cs[3].setup); 62 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 63 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 64 &smc->cs[3].pulse); 65 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 66 &smc->cs[3].cycle); 67 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 68 AT91_SMC_MODE_TDF_CYCLE(2), 69 &smc->cs[3].mode); 70 71 /* Configure RDY/BSY */ 72 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 73 74 /* Enable NandFlash */ 75 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 76 } 77 78 static void smartweb_macb_hw_init(void) 79 { 80 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 81 82 /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ 83 at91_set_gpio_output(AT91_PIN_PA26, 0); 84 85 /* 86 * Disable pull-up on: 87 * RXDV (PA17) => PHY normal mode (not Test mode) 88 * ERX0 (PA14) => PHY ADDR0 89 * ERX1 (PA15) => PHY ADDR1 90 * ERX2 (PA25) => PHY ADDR2 91 * ERX3 (PA26) => PHY ADDR3 92 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 93 * 94 * PHY has internal pull-down 95 */ 96 writel(pin_to_mask(AT91_PIN_PA14) | 97 pin_to_mask(AT91_PIN_PA15) | 98 pin_to_mask(AT91_PIN_PA17) | 99 pin_to_mask(AT91_PIN_PA25) | 100 pin_to_mask(AT91_PIN_PA26) | 101 pin_to_mask(AT91_PIN_PA28) | 102 pin_to_mask(AT91_PIN_PA29), 103 &pioa->pudr); 104 105 at91_phy_reset(); 106 107 /* Re-enable pull-up */ 108 writel(pin_to_mask(AT91_PIN_PA14) | 109 pin_to_mask(AT91_PIN_PA15) | 110 pin_to_mask(AT91_PIN_PA17) | 111 pin_to_mask(AT91_PIN_PA25) | 112 pin_to_mask(AT91_PIN_PA26) | 113 pin_to_mask(AT91_PIN_PA28) | 114 pin_to_mask(AT91_PIN_PA29), 115 &pioa->puer); 116 117 /* Initialize EMAC=MACB hardware */ 118 at91_macb_hw_init(); 119 } 120 121 #ifdef CONFIG_USB_GADGET_AT91 122 #include <linux/usb/at91_udc.h> 123 124 void at91_udp_hw_init(void) 125 { 126 /* Enable PLLB */ 127 at91_pllb_clk_enable(get_pllb_init()); 128 129 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ 130 at91_periph_clk_enable(ATMEL_ID_UDP); 131 132 at91_system_clk_enable(AT91SAM926x_PMC_UDP); 133 } 134 135 struct at91_udc_data board_udc_data = { 136 .baseaddr = ATMEL_BASE_UDP0, 137 }; 138 #endif 139 140 int board_early_init_f(void) 141 { 142 /* enable this here, as we have SPL without serial support */ 143 at91_seriald_hw_init(); 144 smartweb_request_gpio(); 145 return 0; 146 } 147 148 int board_init(void) 149 { 150 smartweb_request_gpio(); 151 /* power LED red */ 152 at91_set_gpio_output(AT91_PIN_PC6, 0); 153 at91_set_gpio_output(AT91_PIN_PC7, 1); 154 /* alarm LED off */ 155 at91_set_gpio_output(AT91_PIN_PC8, 0); 156 at91_set_gpio_output(AT91_PIN_PC9, 0); 157 /* prog LED red */ 158 at91_set_gpio_output(AT91_PIN_PC10, 0); 159 at91_set_gpio_output(AT91_PIN_PC11, 1); 160 161 #ifdef CONFIG_USB_GADGET_AT91 162 at91_udp_hw_init(); 163 at91_udc_probe(&board_udc_data); 164 #endif 165 166 /* Adress of boot parameters */ 167 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 168 169 smartweb_nand_hw_init(); 170 smartweb_macb_hw_init(); 171 return 0; 172 } 173 174 int dram_init(void) 175 { 176 gd->ram_size = get_ram_size( 177 (void *)CONFIG_SYS_SDRAM_BASE, 178 CONFIG_SYS_SDRAM_SIZE); 179 return 0; 180 } 181 182 #ifndef CONFIG_DM_ETH 183 #ifdef CONFIG_MACB 184 int board_eth_init(bd_t *bis) 185 { 186 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); 187 } 188 #endif /* CONFIG_MACB */ 189 #endif 190 191 #if defined(CONFIG_SPL_BUILD) 192 #include <spl.h> 193 #include <nand.h> 194 #include <spi_flash.h> 195 196 void matrix_init(void) 197 { 198 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; 199 200 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) 201 | AT91_MATRIX_SLOT_CYCLE_(0x40), 202 &mat->scfg[3]); 203 } 204 205 void at91_spl_board_init(void) 206 { 207 smartweb_request_gpio(); 208 /* power LED orange */ 209 at91_set_gpio_output(AT91_PIN_PC6, 1); 210 at91_set_gpio_output(AT91_PIN_PC7, 1); 211 /* alarm LED orange */ 212 at91_set_gpio_output(AT91_PIN_PC8, 1); 213 at91_set_gpio_output(AT91_PIN_PC9, 1); 214 /* prog LED red */ 215 at91_set_gpio_output(AT91_PIN_PC10, 0); 216 at91_set_gpio_output(AT91_PIN_PC11, 1); 217 218 smartweb_nand_hw_init(); 219 at91_set_gpio_input(AT91_PIN_PA28, 1); 220 at91_set_gpio_input(AT91_PIN_PA29, 1); 221 222 /* check if both button are pressed */ 223 if (at91_get_gpio_value(AT91_PIN_PA28) == 0 && 224 at91_get_gpio_value(AT91_PIN_PA29) == 0) { 225 smartweb_nand_hw_init(); 226 nand_init(); 227 spl_nand_erase_one(0, 0); 228 } 229 } 230 231 #define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \ 232 | AT91_SDRAMC_CAS_2 \ 233 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ 234 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \ 235 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \ 236 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8)) 237 238 void mem_init(void) 239 { 240 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; 241 struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC; 242 struct sdramc_reg setting; 243 244 setting.cr = SDRAM_BASE_CONF; 245 setting.mdr = AT91_SDRAMC_MD_SDRAM; 246 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; 247 248 /* 249 * I write here directly in this register, because this 250 * approach is smaller than calling at91_set_a_periph() in a 251 * for loop. This saved me 96 bytes. 252 */ 253 writel(0xffff0000, &port->pdr); 254 255 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa); 256 sdramc_initialize(ATMEL_BASE_CS1, &setting); 257 } 258 #endif 259 260 static struct atmel_serial_platdata at91sam9260_serial_plat = { 261 .base_addr = ATMEL_BASE_DBGU, 262 }; 263 264 U_BOOT_DEVICE(at91sam9260_serial) = { 265 .name = "serial_atmel", 266 .platdata = &at91sam9260_serial_plat, 267 }; 268