1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Achim Ehrlich <aehrlich@taskit.de> 7 * taskit GmbH <www.taskit.de> 8 * 9 * (C) Copyright 2012- 10 * Markus Hubig <mhubig@imko.de> 11 * IMKO GmbH <www.imko.de> 12 * (C) Copyright 2014 13 * Heiko Schocher <hs@denx.de> 14 * DENX Software Engineering GmbH 15 * 16 * SPDX-License-Identifier: GPL-2.0+ 17 */ 18 19 #include <common.h> 20 #include <dm.h> 21 #include <asm/io.h> 22 #include <asm/arch/at91sam9_sdramc.h> 23 #include <asm/arch/at91sam9260_matrix.h> 24 #include <asm/arch/at91sam9_smc.h> 25 #include <asm/arch/at91_common.h> 26 #include <asm/arch/atmel_serial.h> 27 #include <asm/arch/at91_spi.h> 28 #include <spi.h> 29 #include <asm/arch/clk.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/gpio.h> 32 #include <watchdog.h> 33 # include <net.h> 34 #ifndef CONFIG_DM_ETH 35 # include <netdev.h> 36 #endif 37 #include <g_dnl.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 static void smartweb_request_gpio(void) 42 { 43 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); 44 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); 45 gpio_request(AT91_PIN_PA26, "ena PHY"); 46 } 47 48 static void smartweb_nand_hw_init(void) 49 { 50 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 51 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 52 unsigned long csa; 53 54 /* Assign CS3 to NAND/SmartMedia Interface */ 55 csa = readl(&matrix->ebicsa); 56 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 57 writel(csa, &matrix->ebicsa); 58 59 /* Configure SMC CS3 for NAND/SmartMedia */ 60 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 61 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 62 &smc->cs[3].setup); 63 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 64 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 65 &smc->cs[3].pulse); 66 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 67 &smc->cs[3].cycle); 68 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 69 AT91_SMC_MODE_TDF_CYCLE(2), 70 &smc->cs[3].mode); 71 72 /* Configure RDY/BSY */ 73 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 74 75 /* Enable NandFlash */ 76 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 77 } 78 79 static void smartweb_macb_hw_init(void) 80 { 81 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 82 83 /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ 84 at91_set_gpio_output(AT91_PIN_PA26, 0); 85 86 /* 87 * Disable pull-up on: 88 * RXDV (PA17) => PHY normal mode (not Test mode) 89 * ERX0 (PA14) => PHY ADDR0 90 * ERX1 (PA15) => PHY ADDR1 91 * ERX2 (PA25) => PHY ADDR2 92 * ERX3 (PA26) => PHY ADDR3 93 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 94 * 95 * PHY has internal pull-down 96 */ 97 writel(pin_to_mask(AT91_PIN_PA14) | 98 pin_to_mask(AT91_PIN_PA15) | 99 pin_to_mask(AT91_PIN_PA17) | 100 pin_to_mask(AT91_PIN_PA25) | 101 pin_to_mask(AT91_PIN_PA26) | 102 pin_to_mask(AT91_PIN_PA28) | 103 pin_to_mask(AT91_PIN_PA29), 104 &pioa->pudr); 105 106 at91_phy_reset(); 107 108 /* Re-enable pull-up */ 109 writel(pin_to_mask(AT91_PIN_PA14) | 110 pin_to_mask(AT91_PIN_PA15) | 111 pin_to_mask(AT91_PIN_PA17) | 112 pin_to_mask(AT91_PIN_PA25) | 113 pin_to_mask(AT91_PIN_PA26) | 114 pin_to_mask(AT91_PIN_PA28) | 115 pin_to_mask(AT91_PIN_PA29), 116 &pioa->puer); 117 118 /* Initialize EMAC=MACB hardware */ 119 at91_macb_hw_init(); 120 } 121 122 #ifdef CONFIG_USB_GADGET_AT91 123 #include <linux/usb/at91_udc.h> 124 125 void at91_udp_hw_init(void) 126 { 127 /* Enable PLLB */ 128 at91_pllb_clk_enable(get_pllb_init()); 129 130 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ 131 at91_periph_clk_enable(ATMEL_ID_UDP); 132 133 at91_system_clk_enable(AT91SAM926x_PMC_UDP); 134 } 135 136 struct at91_udc_data board_udc_data = { 137 .baseaddr = ATMEL_BASE_UDP0, 138 }; 139 #endif 140 141 int board_early_init_f(void) 142 { 143 /* enable this here, as we have SPL without serial support */ 144 at91_seriald_hw_init(); 145 smartweb_request_gpio(); 146 return 0; 147 } 148 149 int board_init(void) 150 { 151 smartweb_request_gpio(); 152 /* power LED red */ 153 at91_set_gpio_output(AT91_PIN_PC6, 0); 154 at91_set_gpio_output(AT91_PIN_PC7, 1); 155 /* alarm LED off */ 156 at91_set_gpio_output(AT91_PIN_PC8, 0); 157 at91_set_gpio_output(AT91_PIN_PC9, 0); 158 /* prog LED red */ 159 at91_set_gpio_output(AT91_PIN_PC10, 0); 160 at91_set_gpio_output(AT91_PIN_PC11, 1); 161 162 #ifdef CONFIG_USB_GADGET_AT91 163 at91_udp_hw_init(); 164 at91_udc_probe(&board_udc_data); 165 #endif 166 167 /* Adress of boot parameters */ 168 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 169 170 smartweb_nand_hw_init(); 171 smartweb_macb_hw_init(); 172 return 0; 173 } 174 175 int dram_init(void) 176 { 177 gd->ram_size = get_ram_size( 178 (void *)CONFIG_SYS_SDRAM_BASE, 179 CONFIG_SYS_SDRAM_SIZE); 180 return 0; 181 } 182 183 #ifndef CONFIG_DM_ETH 184 #ifdef CONFIG_MACB 185 int board_eth_init(bd_t *bis) 186 { 187 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); 188 } 189 #endif /* CONFIG_MACB */ 190 #endif 191 192 #if defined(CONFIG_SPL_BUILD) 193 #include <spl.h> 194 #include <nand.h> 195 #include <spi_flash.h> 196 197 void matrix_init(void) 198 { 199 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; 200 201 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) 202 | AT91_MATRIX_SLOT_CYCLE_(0x40), 203 &mat->scfg[3]); 204 } 205 206 void at91_spl_board_init(void) 207 { 208 smartweb_request_gpio(); 209 /* power LED orange */ 210 at91_set_gpio_output(AT91_PIN_PC6, 1); 211 at91_set_gpio_output(AT91_PIN_PC7, 1); 212 /* alarm LED orange */ 213 at91_set_gpio_output(AT91_PIN_PC8, 1); 214 at91_set_gpio_output(AT91_PIN_PC9, 1); 215 /* prog LED red */ 216 at91_set_gpio_output(AT91_PIN_PC10, 0); 217 at91_set_gpio_output(AT91_PIN_PC11, 1); 218 219 smartweb_nand_hw_init(); 220 at91_set_gpio_input(AT91_PIN_PA28, 1); 221 at91_set_gpio_input(AT91_PIN_PA29, 1); 222 223 /* check if both button are pressed */ 224 if (at91_get_gpio_value(AT91_PIN_PA28) == 0 && 225 at91_get_gpio_value(AT91_PIN_PA29) == 0) { 226 smartweb_nand_hw_init(); 227 nand_init(); 228 spl_nand_erase_one(0, 0); 229 } 230 } 231 232 #define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \ 233 | AT91_SDRAMC_CAS_2 \ 234 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ 235 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \ 236 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \ 237 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8)) 238 239 void mem_init(void) 240 { 241 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; 242 struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC; 243 struct sdramc_reg setting; 244 245 setting.cr = SDRAM_BASE_CONF; 246 setting.mdr = AT91_SDRAMC_MD_SDRAM; 247 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; 248 249 /* 250 * I write here directly in this register, because this 251 * approach is smaller than calling at91_set_a_periph() in a 252 * for loop. This saved me 96 bytes. 253 */ 254 writel(0xffff0000, &port->pdr); 255 256 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa); 257 sdramc_initialize(ATMEL_BASE_CS1, &setting); 258 } 259 #endif 260 261 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) 262 { 263 g_dnl_set_serialnumber("1"); 264 return 0; 265 } 266