1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Achim Ehrlich <aehrlich@taskit.de> 7 * taskit GmbH <www.taskit.de> 8 * 9 * (C) Copyright 2012- 10 * Markus Hubig <mhubig@imko.de> 11 * IMKO GmbH <www.imko.de> 12 * (C) Copyright 2014 13 * Heiko Schocher <hs@denx.de> 14 * DENX Software Engineering GmbH 15 * 16 * SPDX-License-Identifier: GPL-2.0+ 17 */ 18 19 #include <common.h> 20 #include <asm/io.h> 21 #include <asm/arch/at91sam9_sdramc.h> 22 #include <asm/arch/at91sam9260_matrix.h> 23 #include <asm/arch/at91sam9_smc.h> 24 #include <asm/arch/at91_common.h> 25 #include <asm/arch/at91_pmc.h> 26 #include <asm/arch/at91_spi.h> 27 #include <spi.h> 28 #include <asm/arch/clk.h> 29 #include <asm/arch/gpio.h> 30 #include <watchdog.h> 31 #ifdef CONFIG_MACB 32 # include <net.h> 33 # include <netdev.h> 34 #endif 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 static void smartweb_nand_hw_init(void) 39 { 40 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 41 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 42 unsigned long csa; 43 44 /* Assign CS3 to NAND/SmartMedia Interface */ 45 csa = readl(&matrix->ebicsa); 46 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 47 writel(csa, &matrix->ebicsa); 48 49 /* Configure SMC CS3 for NAND/SmartMedia */ 50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 51 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 52 &smc->cs[3].setup); 53 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 54 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 55 &smc->cs[3].pulse); 56 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 57 &smc->cs[3].cycle); 58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 59 AT91_SMC_MODE_TDF_CYCLE(2), 60 &smc->cs[3].mode); 61 62 /* Configure RDY/BSY */ 63 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 64 65 /* Enable NandFlash */ 66 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 67 } 68 69 #ifdef CONFIG_MACB 70 static void smartweb_macb_hw_init(void) 71 { 72 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 73 74 /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ 75 at91_set_gpio_output(AT91_PIN_PA26, 0); 76 77 /* 78 * Disable pull-up on: 79 * RXDV (PA17) => PHY normal mode (not Test mode) 80 * ERX0 (PA14) => PHY ADDR0 81 * ERX1 (PA15) => PHY ADDR1 82 * ERX2 (PA25) => PHY ADDR2 83 * ERX3 (PA26) => PHY ADDR3 84 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 85 * 86 * PHY has internal pull-down 87 */ 88 writel(pin_to_mask(AT91_PIN_PA14) | 89 pin_to_mask(AT91_PIN_PA15) | 90 pin_to_mask(AT91_PIN_PA17) | 91 pin_to_mask(AT91_PIN_PA25) | 92 pin_to_mask(AT91_PIN_PA26) | 93 pin_to_mask(AT91_PIN_PA28), 94 &pioa->pudr); 95 96 at91_phy_reset(); 97 98 /* Re-enable pull-up */ 99 writel(pin_to_mask(AT91_PIN_PA14) | 100 pin_to_mask(AT91_PIN_PA15) | 101 pin_to_mask(AT91_PIN_PA17) | 102 pin_to_mask(AT91_PIN_PA25) | 103 pin_to_mask(AT91_PIN_PA26) | 104 pin_to_mask(AT91_PIN_PA28), 105 &pioa->puer); 106 107 /* Initialize EMAC=MACB hardware */ 108 at91_macb_hw_init(); 109 } 110 #endif /* CONFIG_MACB */ 111 112 #ifdef CONFIG_USB_GADGET_AT91 113 #include <linux/usb/at91_udc.h> 114 115 void at91_udp_hw_init(void) 116 { 117 at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; 118 119 /* Enable PLLB */ 120 writel(get_pllb_init(), &pmc->pllbr); 121 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) 122 ; 123 124 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ 125 at91_periph_clk_enable(ATMEL_ID_UDP); 126 127 writel(AT91SAM926x_PMC_UDP, &pmc->scer); 128 } 129 130 struct at91_udc_data board_udc_data = { 131 .baseaddr = ATMEL_BASE_UDP0, 132 }; 133 #endif 134 135 int board_early_init_f(void) 136 { 137 /* enable this here, as we have SPL without serial support */ 138 at91_seriald_hw_init(); 139 return 0; 140 } 141 142 int board_init(void) 143 { 144 /* Adress of boot parameters */ 145 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 146 147 smartweb_nand_hw_init(); 148 #ifdef CONFIG_MACB 149 smartweb_macb_hw_init(); 150 #endif 151 /* power LED red */ 152 at91_set_gpio_output(AT91_PIN_PC6, 0); 153 at91_set_gpio_output(AT91_PIN_PC7, 1); 154 /* alarm LED off */ 155 at91_set_gpio_output(AT91_PIN_PC8, 0); 156 at91_set_gpio_output(AT91_PIN_PC9, 0); 157 /* prog LED red */ 158 at91_set_gpio_output(AT91_PIN_PC10, 0); 159 at91_set_gpio_output(AT91_PIN_PC11, 1); 160 161 #ifdef CONFIG_USB_GADGET_AT91 162 at91_udp_hw_init(); 163 at91_udc_probe(&board_udc_data); 164 #endif 165 166 return 0; 167 } 168 169 int dram_init(void) 170 { 171 gd->ram_size = get_ram_size( 172 (void *)CONFIG_SYS_SDRAM_BASE, 173 CONFIG_SYS_SDRAM_SIZE); 174 return 0; 175 } 176 177 #ifdef CONFIG_MACB 178 int board_eth_init(bd_t *bis) 179 { 180 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); 181 } 182 #endif /* CONFIG_MACB */ 183 184 #if defined(CONFIG_SPL_BUILD) 185 #include <spl.h> 186 #include <nand.h> 187 #include <spi_flash.h> 188 189 void matrix_init(void) 190 { 191 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; 192 193 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) 194 | AT91_MATRIX_SLOT_CYCLE_(0x40), 195 &mat->scfg[3]); 196 } 197 198 void spl_board_init(void) 199 { 200 at91_set_gpio_output(AT91_PIN_PC6, 1); 201 at91_set_gpio_output(AT91_PIN_PC7, 1); 202 /* alarm LED orange */ 203 at91_set_gpio_output(AT91_PIN_PC8, 1); 204 at91_set_gpio_output(AT91_PIN_PC9, 1); 205 /* prog LED red */ 206 at91_set_gpio_output(AT91_PIN_PC10, 0); 207 at91_set_gpio_output(AT91_PIN_PC11, 1); 208 209 smartweb_nand_hw_init(); 210 at91_set_gpio_input(AT91_PIN_PA28, 1); 211 at91_set_gpio_input(AT91_PIN_PA29, 1); 212 213 /* check if both button are pressed */ 214 if (at91_get_gpio_value(AT91_PIN_PA28) == 0 && 215 at91_get_gpio_value(AT91_PIN_PA29) == 0) { 216 debug("Recovery button pressed\n"); 217 nand_init(); 218 spl_nand_erase_one(0, 0); 219 } 220 } 221 222 #define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \ 223 | AT91_SDRAMC_CAS_2 \ 224 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ 225 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \ 226 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \ 227 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8)) 228 229 void mem_init(void) 230 { 231 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; 232 struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC; 233 struct sdramc_reg setting; 234 235 setting.cr = SDRAM_BASE_CONF; 236 setting.mdr = AT91_SDRAMC_MD_SDRAM; 237 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; 238 239 /* 240 * I write here directly in this register, because this 241 * approach is smaller than calling at91_set_a_periph() in a 242 * for loop. This saved me 96 bytes. 243 */ 244 writel(0xffff0000, &port->pdr); 245 246 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa); 247 sdramc_initialize(ATMEL_BASE_CS1, &setting); 248 } 249 #endif 250