1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Achim Ehrlich <aehrlich@taskit.de> 7 * taskit GmbH <www.taskit.de> 8 * 9 * (C) Copyright 2012- 10 * Markus Hubig <mhubig@imko.de> 11 * IMKO GmbH <www.imko.de> 12 * (C) Copyright 2014 13 * Heiko Schocher <hs@denx.de> 14 * DENX Software Engineering GmbH 15 * 16 * SPDX-License-Identifier: GPL-2.0+ 17 */ 18 19 #include <common.h> 20 #include <asm/io.h> 21 #include <asm/arch/at91sam9_sdramc.h> 22 #include <asm/arch/at91sam9260_matrix.h> 23 #include <asm/arch/at91sam9_smc.h> 24 #include <asm/arch/at91_common.h> 25 #include <asm/arch/at91_spi.h> 26 #include <spi.h> 27 #include <asm/arch/clk.h> 28 #include <asm/arch/gpio.h> 29 #include <watchdog.h> 30 #ifdef CONFIG_MACB 31 # include <net.h> 32 # include <netdev.h> 33 #endif 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static void smartweb_nand_hw_init(void) 38 { 39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 41 unsigned long csa; 42 43 /* Assign CS3 to NAND/SmartMedia Interface */ 44 csa = readl(&matrix->ebicsa); 45 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 46 writel(csa, &matrix->ebicsa); 47 48 /* Configure SMC CS3 for NAND/SmartMedia */ 49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 51 &smc->cs[3].setup); 52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 54 &smc->cs[3].pulse); 55 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 56 &smc->cs[3].cycle); 57 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 58 AT91_SMC_MODE_TDF_CYCLE(2), 59 &smc->cs[3].mode); 60 61 /* Configure RDY/BSY */ 62 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 63 64 /* Enable NandFlash */ 65 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 66 } 67 68 #ifdef CONFIG_MACB 69 static void smartweb_macb_hw_init(void) 70 { 71 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 72 73 /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ 74 at91_set_gpio_output(AT91_PIN_PA26, 0); 75 76 /* 77 * Disable pull-up on: 78 * RXDV (PA17) => PHY normal mode (not Test mode) 79 * ERX0 (PA14) => PHY ADDR0 80 * ERX1 (PA15) => PHY ADDR1 81 * ERX2 (PA25) => PHY ADDR2 82 * ERX3 (PA26) => PHY ADDR3 83 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 84 * 85 * PHY has internal pull-down 86 */ 87 writel(pin_to_mask(AT91_PIN_PA14) | 88 pin_to_mask(AT91_PIN_PA15) | 89 pin_to_mask(AT91_PIN_PA17) | 90 pin_to_mask(AT91_PIN_PA25) | 91 pin_to_mask(AT91_PIN_PA26) | 92 pin_to_mask(AT91_PIN_PA28) | 93 pin_to_mask(AT91_PIN_PA29), 94 &pioa->pudr); 95 96 at91_phy_reset(); 97 98 /* Re-enable pull-up */ 99 writel(pin_to_mask(AT91_PIN_PA14) | 100 pin_to_mask(AT91_PIN_PA15) | 101 pin_to_mask(AT91_PIN_PA17) | 102 pin_to_mask(AT91_PIN_PA25) | 103 pin_to_mask(AT91_PIN_PA26) | 104 pin_to_mask(AT91_PIN_PA28) | 105 pin_to_mask(AT91_PIN_PA29), 106 &pioa->puer); 107 108 /* Initialize EMAC=MACB hardware */ 109 at91_macb_hw_init(); 110 } 111 #endif /* CONFIG_MACB */ 112 113 #ifdef CONFIG_USB_GADGET_AT91 114 #include <linux/usb/at91_udc.h> 115 116 void at91_udp_hw_init(void) 117 { 118 at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; 119 120 /* Enable PLLB */ 121 writel(get_pllb_init(), &pmc->pllbr); 122 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) 123 ; 124 125 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ 126 at91_periph_clk_enable(ATMEL_ID_UDP); 127 128 at91_system_clk_enable(AT91SAM926x_PMC_UDP); 129 } 130 131 struct at91_udc_data board_udc_data = { 132 .baseaddr = ATMEL_BASE_UDP0, 133 }; 134 #endif 135 136 int board_early_init_f(void) 137 { 138 /* enable this here, as we have SPL without serial support */ 139 at91_seriald_hw_init(); 140 return 0; 141 } 142 143 int board_init(void) 144 { 145 /* power LED red */ 146 at91_set_gpio_output(AT91_PIN_PC6, 0); 147 at91_set_gpio_output(AT91_PIN_PC7, 1); 148 /* alarm LED off */ 149 at91_set_gpio_output(AT91_PIN_PC8, 0); 150 at91_set_gpio_output(AT91_PIN_PC9, 0); 151 /* prog LED red */ 152 at91_set_gpio_output(AT91_PIN_PC10, 0); 153 at91_set_gpio_output(AT91_PIN_PC11, 1); 154 155 #ifdef CONFIG_USB_GADGET_AT91 156 at91_udp_hw_init(); 157 at91_udc_probe(&board_udc_data); 158 #endif 159 160 /* Adress of boot parameters */ 161 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 162 163 smartweb_nand_hw_init(); 164 #ifdef CONFIG_MACB 165 smartweb_macb_hw_init(); 166 #endif 167 return 0; 168 } 169 170 int dram_init(void) 171 { 172 gd->ram_size = get_ram_size( 173 (void *)CONFIG_SYS_SDRAM_BASE, 174 CONFIG_SYS_SDRAM_SIZE); 175 return 0; 176 } 177 178 #ifdef CONFIG_MACB 179 int board_eth_init(bd_t *bis) 180 { 181 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); 182 } 183 #endif /* CONFIG_MACB */ 184 185 #if defined(CONFIG_SPL_BUILD) 186 #include <spl.h> 187 #include <nand.h> 188 #include <spi_flash.h> 189 190 void matrix_init(void) 191 { 192 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; 193 194 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) 195 | AT91_MATRIX_SLOT_CYCLE_(0x40), 196 &mat->scfg[3]); 197 } 198 199 void spl_board_init(void) 200 { 201 /* power LED orange */ 202 at91_set_gpio_output(AT91_PIN_PC6, 1); 203 at91_set_gpio_output(AT91_PIN_PC7, 1); 204 /* alarm LED orange */ 205 at91_set_gpio_output(AT91_PIN_PC8, 1); 206 at91_set_gpio_output(AT91_PIN_PC9, 1); 207 /* prog LED red */ 208 at91_set_gpio_output(AT91_PIN_PC10, 0); 209 at91_set_gpio_output(AT91_PIN_PC11, 1); 210 211 smartweb_nand_hw_init(); 212 at91_set_gpio_input(AT91_PIN_PA28, 1); 213 at91_set_gpio_input(AT91_PIN_PA29, 1); 214 215 /* check if both button are pressed */ 216 if (at91_get_gpio_value(AT91_PIN_PA28) == 0 && 217 at91_get_gpio_value(AT91_PIN_PA29) == 0) { 218 smartweb_nand_hw_init(); 219 nand_init(); 220 spl_nand_erase_one(0, 0); 221 } 222 } 223 224 #define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \ 225 | AT91_SDRAMC_CAS_2 \ 226 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ 227 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \ 228 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \ 229 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8)) 230 231 void mem_init(void) 232 { 233 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; 234 struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC; 235 struct sdramc_reg setting; 236 237 setting.cr = SDRAM_BASE_CONF; 238 setting.mdr = AT91_SDRAMC_MD_SDRAM; 239 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; 240 241 /* 242 * I write here directly in this register, because this 243 * approach is smaller than calling at91_set_a_periph() in a 244 * for loop. This saved me 96 bytes. 245 */ 246 writel(0xffff0000, &port->pdr); 247 248 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa); 249 sdramc_initialize(ATMEL_BASE_CS1, &setting); 250 } 251 #endif 252