xref: /openbmc/u-boot/board/siemens/pxm2/pmic.h (revision 459f1da8)
1 /*
2  * (C) Copyright 2013 Siemens Schweiz AG
3  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
4  *
5  * Based on:
6  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 #ifndef PMIC_H
11 #define PMIC_H
12 
13 /*
14  * The PMIC on this board is a TPS65910.
15  */
16 
17 #define PMIC_SR_I2C_ADDR		0x12
18 #define PMIC_CTRL_I2C_ADDR		0x2D
19 /* PMIC Register offsets */
20 #define PMIC_VDD1_REG			0x21
21 #define PMIC_VDD1_OP_REG		0x22
22 #define PMIC_VDD2_REG			0x24
23 #define PMIC_VDD2_OP_REG		0x25
24 #define PMIC_DEVCTRL_REG		0x3f
25 
26 /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
27 #define PMIC_VGAIN_SEL_MASK		(0x3 << 6)
28 #define PMIC_ILMAX_MASK			(0x1 << 5)
29 #define PMIC_TSTEP_MASK			(0x7 << 2)
30 #define PMIC_ST_MASK			(0x3)
31 
32 #define PMIC_REG_VGAIN_SEL_X1		(0x0 << 6)
33 #define PMIC_REG_VGAIN_SEL_X1_0		(0x1 << 6)
34 #define PMIC_REG_VGAIN_SEL_X3		(0x2 << 6)
35 #define PMIC_REG_VGAIN_SEL_X4		(0x3 << 6)
36 
37 #define PMIC_REG_ILMAX_1_0_A		(0x0 << 5)
38 #define PMIC_REG_ILMAX_1_5_A		(0x1 << 5)
39 
40 #define PMIC_REG_TSTEP_			(0x0 << 2)
41 #define PMIC_REG_TSTEP_12_5		(0x1 << 2)
42 #define PMIC_REG_TSTEP_9_4		(0x2 << 2)
43 #define PMIC_REG_TSTEP_7_5		(0x3 << 2)
44 #define PMIC_REG_TSTEP_6_25		(0x4 << 2)
45 #define PMIC_REG_TSTEP_4_7		(0x5 << 2)
46 #define PMIC_REG_TSTEP_3_12		(0x6 << 2)
47 #define PMIC_REG_TSTEP_2_5		(0x7 << 2)
48 
49 #define PMIC_REG_ST_OFF			(0x0)
50 #define PMIC_REG_ST_ON_HI_POW		(0x1)
51 #define PMIC_REG_ST_OFF_1		(0x2)
52 #define PMIC_REG_ST_ON_LOW_POW		(0x3)
53 
54 
55 /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
56 #define PMIC_OP_REG_SEL				(0x7F)
57 
58 #define PMIC_OP_REG_CMD_MASK			(0x1 << 7)
59 #define PMIC_OP_REG_CMD_OP			(0x0 << 7)
60 #define PMIC_OP_REG_CMD_SR			(0x1 << 7)
61 
62 #define PMIC_OP_REG_SEL_MASK			(0x7F)
63 #define PMIC_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
64 #define PMIC_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
65 
66 /* Device control register . (DEVCTRL_REG) */
67 #define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK	(0x1 << 4)
68 #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
69 #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
70 
71 #endif
72