xref: /openbmc/u-boot/board/siemens/pxm2/pmic.h (revision c0dcece7)
1*c0dcece7SHeiko Schocher /*
2*c0dcece7SHeiko Schocher  * (C) Copyright 2013 Siemens Schweiz AG
3*c0dcece7SHeiko Schocher  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
4*c0dcece7SHeiko Schocher  *
5*c0dcece7SHeiko Schocher  * Based on:
6*c0dcece7SHeiko Schocher  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7*c0dcece7SHeiko Schocher  *
8*c0dcece7SHeiko Schocher  * SPDX-License-Identifier:	GPL-2.0+
9*c0dcece7SHeiko Schocher  */
10*c0dcece7SHeiko Schocher #ifndef PMIC_H
11*c0dcece7SHeiko Schocher #define PMIC_H
12*c0dcece7SHeiko Schocher 
13*c0dcece7SHeiko Schocher /*
14*c0dcece7SHeiko Schocher  * The PMIC on this board is a TPS65910.
15*c0dcece7SHeiko Schocher  */
16*c0dcece7SHeiko Schocher 
17*c0dcece7SHeiko Schocher #define PMIC_SR_I2C_ADDR		0x12
18*c0dcece7SHeiko Schocher #define PMIC_CTRL_I2C_ADDR		0x2D
19*c0dcece7SHeiko Schocher /* PMIC Register offsets */
20*c0dcece7SHeiko Schocher #define PMIC_VDD1_REG			0x21
21*c0dcece7SHeiko Schocher #define PMIC_VDD1_OP_REG		0x22
22*c0dcece7SHeiko Schocher #define PMIC_VDD2_REG			0x24
23*c0dcece7SHeiko Schocher #define PMIC_VDD2_OP_REG		0x25
24*c0dcece7SHeiko Schocher #define PMIC_DEVCTRL_REG		0x3f
25*c0dcece7SHeiko Schocher 
26*c0dcece7SHeiko Schocher /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
27*c0dcece7SHeiko Schocher #define PMIC_VGAIN_SEL_MASK		(0x3 << 6)
28*c0dcece7SHeiko Schocher #define PMIC_ILMAX_MASK			(0x1 << 5)
29*c0dcece7SHeiko Schocher #define PMIC_TSTEP_MASK			(0x7 << 2)
30*c0dcece7SHeiko Schocher #define PMIC_ST_MASK			(0x3)
31*c0dcece7SHeiko Schocher 
32*c0dcece7SHeiko Schocher #define PMIC_REG_VGAIN_SEL_X1		(0x0 << 6)
33*c0dcece7SHeiko Schocher #define PMIC_REG_VGAIN_SEL_X1_0		(0x1 << 6)
34*c0dcece7SHeiko Schocher #define PMIC_REG_VGAIN_SEL_X3		(0x2 << 6)
35*c0dcece7SHeiko Schocher #define PMIC_REG_VGAIN_SEL_X4		(0x3 << 6)
36*c0dcece7SHeiko Schocher 
37*c0dcece7SHeiko Schocher #define PMIC_REG_ILMAX_1_0_A		(0x0 << 5)
38*c0dcece7SHeiko Schocher #define PMIC_REG_ILMAX_1_5_A		(0x1 << 5)
39*c0dcece7SHeiko Schocher 
40*c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_			(0x0 << 2)
41*c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_12_5		(0x1 << 2)
42*c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_9_4		(0x2 << 2)
43*c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_7_5		(0x3 << 2)
44*c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_6_25		(0x4 << 2)
45*c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_4_7		(0x5 << 2)
46*c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_3_12		(0x6 << 2)
47*c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_2_5		(0x7 << 2)
48*c0dcece7SHeiko Schocher 
49*c0dcece7SHeiko Schocher #define PMIC_REG_ST_OFF			(0x0)
50*c0dcece7SHeiko Schocher #define PMIC_REG_ST_ON_HI_POW		(0x1)
51*c0dcece7SHeiko Schocher #define PMIC_REG_ST_OFF_1		(0x2)
52*c0dcece7SHeiko Schocher #define PMIC_REG_ST_ON_LOW_POW		(0x3)
53*c0dcece7SHeiko Schocher 
54*c0dcece7SHeiko Schocher 
55*c0dcece7SHeiko Schocher /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
56*c0dcece7SHeiko Schocher #define PMIC_OP_REG_SEL				(0x7F)
57*c0dcece7SHeiko Schocher 
58*c0dcece7SHeiko Schocher #define PMIC_OP_REG_CMD_MASK			(0x1 << 7)
59*c0dcece7SHeiko Schocher #define PMIC_OP_REG_CMD_OP			(0x0 << 7)
60*c0dcece7SHeiko Schocher #define PMIC_OP_REG_CMD_SR			(0x1 << 7)
61*c0dcece7SHeiko Schocher 
62*c0dcece7SHeiko Schocher #define PMIC_OP_REG_SEL_MASK			(0x7F)
63*c0dcece7SHeiko Schocher #define PMIC_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
64*c0dcece7SHeiko Schocher #define PMIC_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
65*c0dcece7SHeiko Schocher 
66*c0dcece7SHeiko Schocher /* Device control register . (DEVCTRL_REG) */
67*c0dcece7SHeiko Schocher #define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK	(0x1 << 4)
68*c0dcece7SHeiko Schocher #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
69*c0dcece7SHeiko Schocher #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
70*c0dcece7SHeiko Schocher 
71*c0dcece7SHeiko Schocher #endif
72