xref: /openbmc/u-boot/board/siemens/pxm2/pmic.h (revision e8f80a5a)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2c0dcece7SHeiko Schocher /*
3c0dcece7SHeiko Schocher  * (C) Copyright 2013 Siemens Schweiz AG
4c0dcece7SHeiko Schocher  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
5c0dcece7SHeiko Schocher  *
6c0dcece7SHeiko Schocher  * Based on:
7c0dcece7SHeiko Schocher  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8c0dcece7SHeiko Schocher  */
9c0dcece7SHeiko Schocher #ifndef PMIC_H
10c0dcece7SHeiko Schocher #define PMIC_H
11c0dcece7SHeiko Schocher 
12c0dcece7SHeiko Schocher /*
13c0dcece7SHeiko Schocher  * The PMIC on this board is a TPS65910.
14c0dcece7SHeiko Schocher  */
15c0dcece7SHeiko Schocher 
16c0dcece7SHeiko Schocher #define PMIC_SR_I2C_ADDR		0x12
17c0dcece7SHeiko Schocher #define PMIC_CTRL_I2C_ADDR		0x2D
18c0dcece7SHeiko Schocher /* PMIC Register offsets */
19c0dcece7SHeiko Schocher #define PMIC_VDD1_REG			0x21
20c0dcece7SHeiko Schocher #define PMIC_VDD1_OP_REG		0x22
21c0dcece7SHeiko Schocher #define PMIC_VDD2_REG			0x24
22c0dcece7SHeiko Schocher #define PMIC_VDD2_OP_REG		0x25
23c0dcece7SHeiko Schocher #define PMIC_DEVCTRL_REG		0x3f
24c0dcece7SHeiko Schocher 
25c0dcece7SHeiko Schocher /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
26c0dcece7SHeiko Schocher #define PMIC_VGAIN_SEL_MASK		(0x3 << 6)
27c0dcece7SHeiko Schocher #define PMIC_ILMAX_MASK			(0x1 << 5)
28c0dcece7SHeiko Schocher #define PMIC_TSTEP_MASK			(0x7 << 2)
29c0dcece7SHeiko Schocher #define PMIC_ST_MASK			(0x3)
30c0dcece7SHeiko Schocher 
31c0dcece7SHeiko Schocher #define PMIC_REG_VGAIN_SEL_X1		(0x0 << 6)
32c0dcece7SHeiko Schocher #define PMIC_REG_VGAIN_SEL_X1_0		(0x1 << 6)
33c0dcece7SHeiko Schocher #define PMIC_REG_VGAIN_SEL_X3		(0x2 << 6)
34c0dcece7SHeiko Schocher #define PMIC_REG_VGAIN_SEL_X4		(0x3 << 6)
35c0dcece7SHeiko Schocher 
36c0dcece7SHeiko Schocher #define PMIC_REG_ILMAX_1_0_A		(0x0 << 5)
37c0dcece7SHeiko Schocher #define PMIC_REG_ILMAX_1_5_A		(0x1 << 5)
38c0dcece7SHeiko Schocher 
39c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_			(0x0 << 2)
40c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_12_5		(0x1 << 2)
41c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_9_4		(0x2 << 2)
42c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_7_5		(0x3 << 2)
43c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_6_25		(0x4 << 2)
44c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_4_7		(0x5 << 2)
45c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_3_12		(0x6 << 2)
46c0dcece7SHeiko Schocher #define PMIC_REG_TSTEP_2_5		(0x7 << 2)
47c0dcece7SHeiko Schocher 
48c0dcece7SHeiko Schocher #define PMIC_REG_ST_OFF			(0x0)
49c0dcece7SHeiko Schocher #define PMIC_REG_ST_ON_HI_POW		(0x1)
50c0dcece7SHeiko Schocher #define PMIC_REG_ST_OFF_1		(0x2)
51c0dcece7SHeiko Schocher #define PMIC_REG_ST_ON_LOW_POW		(0x3)
52c0dcece7SHeiko Schocher 
53c0dcece7SHeiko Schocher 
54c0dcece7SHeiko Schocher /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
55c0dcece7SHeiko Schocher #define PMIC_OP_REG_SEL				(0x7F)
56c0dcece7SHeiko Schocher 
57c0dcece7SHeiko Schocher #define PMIC_OP_REG_CMD_MASK			(0x1 << 7)
58c0dcece7SHeiko Schocher #define PMIC_OP_REG_CMD_OP			(0x0 << 7)
59c0dcece7SHeiko Schocher #define PMIC_OP_REG_CMD_SR			(0x1 << 7)
60c0dcece7SHeiko Schocher 
61c0dcece7SHeiko Schocher #define PMIC_OP_REG_SEL_MASK			(0x7F)
62c0dcece7SHeiko Schocher #define PMIC_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
63c0dcece7SHeiko Schocher #define PMIC_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
64c0dcece7SHeiko Schocher 
65c0dcece7SHeiko Schocher /* Device control register . (DEVCTRL_REG) */
66c0dcece7SHeiko Schocher #define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK	(0x1 << 4)
67c0dcece7SHeiko Schocher #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
68c0dcece7SHeiko Schocher #define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
69c0dcece7SHeiko Schocher 
70c0dcece7SHeiko Schocher #endif
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