1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * pinmux setup for siemens pxm2 board 4 * 5 * (C) Copyright 2013 Siemens Schweiz AG 6 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. 7 * 8 * Based on: 9 * u-boot:/board/ti/am335x/mux.c 10 * 11 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 12 */ 13 14 #include <common.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/mux.h> 18 #include <asm/io.h> 19 #include <i2c.h> 20 #include "board.h" 21 22 static struct module_pin_mux uart0_pin_mux[] = { 23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 25 {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */ 26 {-1}, 27 }; 28 29 #ifdef CONFIG_NAND 30 static struct module_pin_mux nand_pin_mux[] = { 31 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 32 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 33 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 34 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 35 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 36 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 37 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 38 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 39 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 40 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 41 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 42 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 43 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 44 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 45 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 46 {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */ 47 {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */ 48 {-1}, 49 }; 50 #endif 51 52 static struct module_pin_mux i2c0_pin_mux[] = { 53 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, 54 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, 55 {-1}, 56 }; 57 58 static struct module_pin_mux i2c1_pin_mux[] = { 59 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, 60 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, 61 {-1}, 62 }; 63 64 #ifndef CONFIG_NO_ETH 65 static struct module_pin_mux rgmii1_pin_mux[] = { 66 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ 67 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 68 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ 69 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ 70 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ 71 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ 72 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ 73 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 74 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 75 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 76 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 77 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 78 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 79 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 80 {-1}, 81 }; 82 83 static struct module_pin_mux rgmii2_pin_mux[] = { 84 {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */ 85 {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */ 86 {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */ 87 {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */ 88 {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */ 89 {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */ 90 {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */ 91 {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */ 92 {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */ 93 {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */ 94 {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */ 95 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 96 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 97 {-1}, 98 }; 99 #endif 100 101 #ifdef CONFIG_MMC 102 static struct module_pin_mux mmc0_pin_mux[] = { 103 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 104 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 105 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 106 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 107 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 108 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 109 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ 110 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */ 111 {-1}, 112 }; 113 #endif 114 115 static struct module_pin_mux lcdc_pin_mux[] = { 116 {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */ 117 {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */ 118 {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */ 119 {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */ 120 {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */ 121 {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */ 122 {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */ 123 {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */ 124 {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */ 125 {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */ 126 {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */ 127 {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */ 128 {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */ 129 {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */ 130 {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */ 131 {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */ 132 {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */ 133 {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */ 134 {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */ 135 {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */ 136 {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */ 137 {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */ 138 {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */ 139 {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */ 140 {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */ 141 {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */ 142 {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */ 143 {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */ 144 {-1}, 145 }; 146 147 static struct module_pin_mux ecap0_pin_mux[] = { 148 {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, 149 {-1}, 150 }; 151 152 static struct module_pin_mux gpio_pin_mux[] = { 153 {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/ 154 {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */ 155 {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */ 156 {-1}, 157 }; 158 void enable_i2c0_pin_mux(void) 159 { 160 configure_module_pin_mux(i2c0_pin_mux); 161 } 162 163 void enable_uart0_pin_mux(void) 164 { 165 configure_module_pin_mux(uart0_pin_mux); 166 } 167 168 void enable_board_pin_mux(void) 169 { 170 configure_module_pin_mux(uart0_pin_mux); 171 configure_module_pin_mux(i2c1_pin_mux); 172 #ifdef CONFIG_NAND 173 configure_module_pin_mux(nand_pin_mux); 174 #endif 175 #ifndef CONFIG_NO_ETH 176 configure_module_pin_mux(rgmii1_pin_mux); 177 configure_module_pin_mux(rgmii2_pin_mux); 178 #endif 179 #ifdef CONFIG_MMC 180 configure_module_pin_mux(mmc0_pin_mux); 181 #endif 182 configure_module_pin_mux(lcdc_pin_mux); 183 configure_module_pin_mux(gpio_pin_mux); 184 configure_module_pin_mux(ecap0_pin_mux); 185 } 186