1 /* 2 * Board functions for Siemens CORVUS (AT91SAM9G45) based board 3 * (C) Copyright 2013 Siemens AG 4 * 5 * Based on: 6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 15 #include <common.h> 16 #include <asm/io.h> 17 #include <asm/arch/at91sam9g45_matrix.h> 18 #include <asm/arch/at91sam9_smc.h> 19 #include <asm/arch/at91_common.h> 20 #include <asm/arch/at91_pmc.h> 21 #include <asm/arch/at91_rstc.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/clk.h> 24 #include <lcd.h> 25 #include <atmel_lcdc.h> 26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 27 #include <net.h> 28 #endif 29 #include <netdev.h> 30 #include <spi.h> 31 32 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 33 #include <asm/arch/atmel_usba_udc.h> 34 #endif 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 static void corvus_nand_hw_init(void) 39 { 40 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 41 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 42 unsigned long csa; 43 44 /* Enable CS3 */ 45 csa = readl(&matrix->ebicsa); 46 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 47 writel(csa, &matrix->ebicsa); 48 49 /* Configure SMC CS3 for NAND/SmartMedia */ 50 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 51 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 52 &smc->cs[3].setup); 53 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | 54 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), 55 &smc->cs[3].pulse); 56 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 57 &smc->cs[3].cycle); 58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 59 AT91_SMC_MODE_EXNW_DISABLE | 60 #ifdef CONFIG_SYS_NAND_DBW_16 61 AT91_SMC_MODE_DBW_16 | 62 #else /* CONFIG_SYS_NAND_DBW_8 */ 63 AT91_SMC_MODE_DBW_8 | 64 #endif 65 AT91_SMC_MODE_TDF_CYCLE(3), 66 &smc->cs[3].mode); 67 68 at91_periph_clk_enable(ATMEL_ID_PIOC); 69 at91_periph_clk_enable(ATMEL_ID_PIOA); 70 71 /* Enable NandFlash */ 72 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 73 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 74 } 75 76 #if defined(CONFIG_SPL_BUILD) 77 #include <spl.h> 78 #include <nand.h> 79 80 void spl_board_init(void) 81 { 82 /* 83 * For on the sam9m10g45ek board, the chip wm9711 stay in the test 84 * mode, so it need do some action to exit mode. 85 */ 86 at91_set_gpio_output(AT91_PIN_PD7, 0); 87 at91_set_gpio_output(AT91_PIN_PD8, 0); 88 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); 89 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); 90 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 91 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 92 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 93 94 corvus_nand_hw_init(); 95 96 /* Configure recovery button PINs */ 97 at91_set_gpio_input(AT91_PIN_PB7, 1); 98 99 /* check if button is pressed */ 100 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { 101 u32 boot_device; 102 103 debug("Recovery button pressed\n"); 104 boot_device = spl_boot_device(); 105 switch (boot_device) { 106 #ifdef CONFIG_SPL_NAND_SUPPORT 107 case BOOT_DEVICE_NAND: 108 nand_init(); 109 spl_nand_erase_one(0, 0); 110 break; 111 #endif 112 } 113 } 114 } 115 116 #include <asm/arch/atmel_mpddrc.h> 117 static void ddr2_conf(struct atmel_mpddr *ddr2) 118 { 119 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 120 121 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 122 ATMEL_MPDDRC_CR_NR_ROW_14 | 123 ATMEL_MPDDRC_CR_DIC_DS | 124 ATMEL_MPDDRC_CR_DQMS_SHARED | 125 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 126 ddr2->rtr = 0x24b; 127 128 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 129 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 130 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 131 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ 132 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 133 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 134 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 135 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 136 137 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 138 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 139 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 140 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 141 142 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 143 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 144 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 145 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 146 } 147 148 void mem_init(void) 149 { 150 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 151 struct atmel_mpddr ddr2; 152 153 ddr2_conf(&ddr2); 154 155 /* enable DDR2 clock */ 156 writel(AT91_PMC_DDR, &pmc->scer); 157 158 /* DDRAM2 Controller initialize */ 159 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); 160 } 161 #endif 162 163 #ifdef CONFIG_CMD_USB 164 static void taurus_usb_hw_init(void) 165 { 166 at91_periph_clk_enable(ATMEL_ID_PIODE); 167 168 at91_set_gpio_output(AT91_PIN_PD1, 0); 169 at91_set_gpio_output(AT91_PIN_PD3, 0); 170 } 171 #endif 172 173 #ifdef CONFIG_MACB 174 static void corvus_macb_hw_init(void) 175 { 176 /* Enable clock */ 177 at91_periph_clk_enable(ATMEL_ID_EMAC); 178 179 /* 180 * Disable pull-up on: 181 * RXDV (PA15) => PHY normal mode (not Test mode) 182 * ERX0 (PA12) => PHY ADDR0 183 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 184 * 185 * PHY has internal pull-down 186 */ 187 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 188 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); 189 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); 190 191 at91_phy_reset(); 192 193 /* Re-enable pull-up */ 194 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 195 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 196 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 197 198 /* And the pins. */ 199 at91_macb_hw_init(); 200 } 201 #endif 202 203 int board_early_init_f(void) 204 { 205 at91_seriald_hw_init(); 206 return 0; 207 } 208 209 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 210 /* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */ 211 void at91_udp_hw_init(void) 212 { 213 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 214 215 /* Enable UPLL clock */ 216 writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); 217 /* Enable UDPHS clock */ 218 at91_periph_clk_enable(ATMEL_ID_UDPHS); 219 } 220 #endif 221 222 int board_init(void) 223 { 224 /* address of boot parameters */ 225 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 226 227 #ifdef CONFIG_CMD_NAND 228 corvus_nand_hw_init(); 229 #endif 230 #ifdef CONFIG_ATMEL_SPI 231 at91_spi0_hw_init(1 << 4); 232 #endif 233 #ifdef CONFIG_HAS_DATAFLASH 234 at91_spi0_hw_init(1 << 0); 235 #endif 236 #ifdef CONFIG_MACB 237 corvus_macb_hw_init(); 238 #endif 239 #ifdef CONFIG_CMD_USB 240 taurus_usb_hw_init(); 241 #endif 242 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 243 at91_udp_hw_init(); 244 usba_udc_probe(&pdata); 245 #endif 246 return 0; 247 } 248 249 int dram_init(void) 250 { 251 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 252 CONFIG_SYS_SDRAM_SIZE); 253 return 0; 254 } 255 256 int board_eth_init(bd_t *bis) 257 { 258 int rc = 0; 259 #ifdef CONFIG_MACB 260 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 261 #endif 262 return rc; 263 } 264 265 /* SPI chip select control */ 266 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 267 { 268 return bus == 0 && cs < 2; 269 } 270 271 void spi_cs_activate(struct spi_slave *slave) 272 { 273 switch (slave->cs) { 274 case 1: 275 at91_set_gpio_output(AT91_PIN_PB18, 0); 276 break; 277 case 0: 278 default: 279 at91_set_gpio_output(AT91_PIN_PB3, 0); 280 break; 281 } 282 } 283 284 void spi_cs_deactivate(struct spi_slave *slave) 285 { 286 switch (slave->cs) { 287 case 1: 288 at91_set_gpio_output(AT91_PIN_PB18, 1); 289 break; 290 case 0: 291 default: 292 at91_set_gpio_output(AT91_PIN_PB3, 1); 293 break; 294 } 295 } 296