1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Board functions for Siemens CORVUS (AT91SAM9G45) based board 4 * (C) Copyright 2013 Siemens AG 5 * 6 * Based on: 7 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c 8 * (C) Copyright 2007-2008 9 * Stelian Pop <stelian@popies.net> 10 * Lead Tech Design <www.leadtechdesign.com> 11 */ 12 13 #include <common.h> 14 #include <dm.h> 15 #include <asm/io.h> 16 #include <asm/arch/at91sam9g45_matrix.h> 17 #include <asm/arch/at91sam9_smc.h> 18 #include <asm/arch/at91_common.h> 19 #include <asm/arch/at91_rstc.h> 20 #include <asm/arch/atmel_serial.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/gpio.h> 23 #include <asm/arch/clk.h> 24 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 25 #include <net.h> 26 #endif 27 #ifndef CONFIG_DM_ETH 28 #include <netdev.h> 29 #endif 30 #include <spi.h> 31 32 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 33 #include <asm/arch/atmel_usba_udc.h> 34 #endif 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 static void corvus_request_gpio(void) 39 { 40 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); 41 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); 42 gpio_request(AT91_PIN_PD7, "d0"); 43 gpio_request(AT91_PIN_PD8, "d1"); 44 gpio_request(AT91_PIN_PA12, "d2"); 45 gpio_request(AT91_PIN_PA13, "d3"); 46 gpio_request(AT91_PIN_PA15, "d4"); 47 gpio_request(AT91_PIN_PB7, "recovery button"); 48 gpio_request(AT91_PIN_PD1, "USB0"); 49 gpio_request(AT91_PIN_PD3, "USB1"); 50 gpio_request(AT91_PIN_PB18, "SPICS1"); 51 gpio_request(AT91_PIN_PB3, "SPICS0"); 52 gpio_request(CONFIG_RED_LED, "red led"); 53 gpio_request(CONFIG_GREEN_LED, "green led"); 54 } 55 56 static void corvus_nand_hw_init(void) 57 { 58 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 59 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 60 unsigned long csa; 61 62 /* Enable CS3 */ 63 csa = readl(&matrix->ebicsa); 64 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 65 writel(csa, &matrix->ebicsa); 66 67 /* Configure SMC CS3 for NAND/SmartMedia */ 68 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 69 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 70 &smc->cs[3].setup); 71 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | 72 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), 73 &smc->cs[3].pulse); 74 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 75 &smc->cs[3].cycle); 76 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 77 AT91_SMC_MODE_EXNW_DISABLE | 78 #ifdef CONFIG_SYS_NAND_DBW_16 79 AT91_SMC_MODE_DBW_16 | 80 #else /* CONFIG_SYS_NAND_DBW_8 */ 81 AT91_SMC_MODE_DBW_8 | 82 #endif 83 AT91_SMC_MODE_TDF_CYCLE(3), 84 &smc->cs[3].mode); 85 86 at91_periph_clk_enable(ATMEL_ID_PIOC); 87 at91_periph_clk_enable(ATMEL_ID_PIOA); 88 89 /* Enable NandFlash */ 90 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 91 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 92 } 93 94 #if defined(CONFIG_SPL_BUILD) 95 #include <spl.h> 96 #include <nand.h> 97 98 void spl_board_init(void) 99 { 100 corvus_request_gpio(); 101 /* 102 * For on the sam9m10g45ek board, the chip wm9711 stay in the test 103 * mode, so it need do some action to exit mode. 104 */ 105 at91_set_gpio_output(AT91_PIN_PD7, 0); 106 at91_set_gpio_output(AT91_PIN_PD8, 0); 107 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); 108 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); 109 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 110 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 111 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 112 113 corvus_nand_hw_init(); 114 115 /* Configure recovery button PINs */ 116 at91_set_gpio_input(AT91_PIN_PB7, 1); 117 118 /* check if button is pressed */ 119 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { 120 u32 boot_device; 121 122 debug("Recovery button pressed\n"); 123 boot_device = spl_boot_device(); 124 switch (boot_device) { 125 #ifdef CONFIG_SPL_NAND_SUPPORT 126 case BOOT_DEVICE_NAND: 127 nand_init(); 128 spl_nand_erase_one(0, 0); 129 break; 130 #endif 131 } 132 } 133 } 134 135 #include <asm/arch/atmel_mpddrc.h> 136 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 137 { 138 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 139 140 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 141 ATMEL_MPDDRC_CR_NR_ROW_14 | 142 ATMEL_MPDDRC_CR_DIC_DS | 143 ATMEL_MPDDRC_CR_DQMS_SHARED | 144 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 145 ddr2->rtr = 0x24b; 146 147 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 148 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 149 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 150 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ 151 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 152 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 153 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 154 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 155 156 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 157 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 158 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 159 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 160 161 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 162 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 163 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 164 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 165 } 166 167 void mem_init(void) 168 { 169 struct atmel_mpddrc_config ddr2; 170 171 ddr2_conf(&ddr2); 172 173 at91_system_clk_enable(AT91_PMC_DDR); 174 175 /* DDRAM2 Controller initialize */ 176 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); 177 } 178 #endif 179 180 #ifdef CONFIG_CMD_USB 181 static void taurus_usb_hw_init(void) 182 { 183 at91_periph_clk_enable(ATMEL_ID_PIODE); 184 185 at91_set_gpio_output(AT91_PIN_PD1, 0); 186 at91_set_gpio_output(AT91_PIN_PD3, 0); 187 } 188 #endif 189 190 #ifdef CONFIG_MACB 191 static void corvus_macb_hw_init(void) 192 { 193 /* Enable clock */ 194 at91_periph_clk_enable(ATMEL_ID_EMAC); 195 196 /* 197 * Disable pull-up on: 198 * RXDV (PA15) => PHY normal mode (not Test mode) 199 * ERX0 (PA12) => PHY ADDR0 200 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 201 * 202 * PHY has internal pull-down 203 */ 204 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 205 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); 206 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); 207 208 at91_phy_reset(); 209 210 /* Re-enable pull-up */ 211 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 212 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 213 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 214 215 /* And the pins. */ 216 at91_macb_hw_init(); 217 } 218 #endif 219 220 int board_early_init_f(void) 221 { 222 at91_seriald_hw_init(); 223 corvus_request_gpio(); 224 return 0; 225 } 226 227 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 228 /* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */ 229 void at91_udp_hw_init(void) 230 { 231 /* Enable UPLL clock */ 232 at91_upll_clk_enable(); 233 234 /* Enable UDPHS clock */ 235 at91_periph_clk_enable(ATMEL_ID_UDPHS); 236 } 237 #endif 238 239 int board_init(void) 240 { 241 /* address of boot parameters */ 242 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 243 244 /* we have to request the gpios again after relocation */ 245 corvus_request_gpio(); 246 #ifdef CONFIG_CMD_NAND 247 corvus_nand_hw_init(); 248 #endif 249 #ifdef CONFIG_ATMEL_SPI 250 at91_spi0_hw_init(1 << 4); 251 #endif 252 #ifdef CONFIG_MACB 253 corvus_macb_hw_init(); 254 #endif 255 #ifdef CONFIG_CMD_USB 256 taurus_usb_hw_init(); 257 #endif 258 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 259 at91_udp_hw_init(); 260 usba_udc_probe(&pdata); 261 #endif 262 return 0; 263 } 264 265 int dram_init(void) 266 { 267 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 268 CONFIG_SYS_SDRAM_SIZE); 269 return 0; 270 } 271 272 #ifndef CONFIG_DM_ETH 273 int board_eth_init(bd_t *bis) 274 { 275 int rc = 0; 276 #ifdef CONFIG_MACB 277 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 278 #endif 279 return rc; 280 } 281 #endif 282 283 /* SPI chip select control */ 284 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 285 { 286 return bus == 0 && cs < 2; 287 } 288 289 void spi_cs_activate(struct spi_slave *slave) 290 { 291 switch (slave->cs) { 292 case 1: 293 at91_set_gpio_output(AT91_PIN_PB18, 0); 294 break; 295 case 0: 296 default: 297 at91_set_gpio_output(AT91_PIN_PB3, 0); 298 break; 299 } 300 } 301 302 void spi_cs_deactivate(struct spi_slave *slave) 303 { 304 switch (slave->cs) { 305 case 1: 306 at91_set_gpio_output(AT91_PIN_PB18, 1); 307 break; 308 case 0: 309 default: 310 at91_set_gpio_output(AT91_PIN_PB3, 1); 311 break; 312 } 313 } 314 315 static struct atmel_serial_platdata at91sam9260_serial_plat = { 316 .base_addr = ATMEL_BASE_DBGU, 317 }; 318 319 U_BOOT_DEVICE(at91sam9260_serial) = { 320 .name = "serial_atmel", 321 .platdata = &at91sam9260_serial_plat, 322 }; 323