1 /* 2 * Board functions for Siemens CORVUS (AT91SAM9G45) based board 3 * (C) Copyright 2013 Siemens AG 4 * 5 * Based on: 6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 15 #include <common.h> 16 #include <asm/io.h> 17 #include <asm/arch/at91sam9g45_matrix.h> 18 #include <asm/arch/at91sam9_smc.h> 19 #include <asm/arch/at91_common.h> 20 #include <asm/arch/at91_rstc.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/clk.h> 23 #include <lcd.h> 24 #include <atmel_lcdc.h> 25 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 26 #include <net.h> 27 #endif 28 #include <netdev.h> 29 #include <spi.h> 30 31 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 32 #include <asm/arch/atmel_usba_udc.h> 33 #endif 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static void corvus_nand_hw_init(void) 38 { 39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 41 unsigned long csa; 42 43 /* Enable CS3 */ 44 csa = readl(&matrix->ebicsa); 45 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 46 writel(csa, &matrix->ebicsa); 47 48 /* Configure SMC CS3 for NAND/SmartMedia */ 49 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 50 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 51 &smc->cs[3].setup); 52 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | 53 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), 54 &smc->cs[3].pulse); 55 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 56 &smc->cs[3].cycle); 57 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 58 AT91_SMC_MODE_EXNW_DISABLE | 59 #ifdef CONFIG_SYS_NAND_DBW_16 60 AT91_SMC_MODE_DBW_16 | 61 #else /* CONFIG_SYS_NAND_DBW_8 */ 62 AT91_SMC_MODE_DBW_8 | 63 #endif 64 AT91_SMC_MODE_TDF_CYCLE(3), 65 &smc->cs[3].mode); 66 67 at91_periph_clk_enable(ATMEL_ID_PIOC); 68 at91_periph_clk_enable(ATMEL_ID_PIOA); 69 70 /* Enable NandFlash */ 71 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 72 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 73 } 74 75 #if defined(CONFIG_SPL_BUILD) 76 #include <spl.h> 77 #include <nand.h> 78 79 void spl_board_init(void) 80 { 81 /* 82 * For on the sam9m10g45ek board, the chip wm9711 stay in the test 83 * mode, so it need do some action to exit mode. 84 */ 85 at91_set_gpio_output(AT91_PIN_PD7, 0); 86 at91_set_gpio_output(AT91_PIN_PD8, 0); 87 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); 88 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); 89 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 90 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 91 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 92 93 corvus_nand_hw_init(); 94 95 /* Configure recovery button PINs */ 96 at91_set_gpio_input(AT91_PIN_PB7, 1); 97 98 /* check if button is pressed */ 99 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { 100 u32 boot_device; 101 102 debug("Recovery button pressed\n"); 103 boot_device = spl_boot_device(); 104 switch (boot_device) { 105 #ifdef CONFIG_SPL_NAND_SUPPORT 106 case BOOT_DEVICE_NAND: 107 nand_init(); 108 spl_nand_erase_one(0, 0); 109 break; 110 #endif 111 } 112 } 113 } 114 115 #include <asm/arch/atmel_mpddrc.h> 116 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 117 { 118 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 119 120 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 121 ATMEL_MPDDRC_CR_NR_ROW_14 | 122 ATMEL_MPDDRC_CR_DIC_DS | 123 ATMEL_MPDDRC_CR_DQMS_SHARED | 124 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 125 ddr2->rtr = 0x24b; 126 127 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 128 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 129 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 130 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ 131 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 132 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 133 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 134 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 135 136 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 137 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 138 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 139 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 140 141 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 142 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 143 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 144 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 145 } 146 147 void mem_init(void) 148 { 149 struct atmel_mpddrc_config ddr2; 150 151 ddr2_conf(&ddr2); 152 153 at91_system_clk_enable(AT91_PMC_DDR); 154 155 /* DDRAM2 Controller initialize */ 156 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); 157 } 158 #endif 159 160 #ifdef CONFIG_CMD_USB 161 static void taurus_usb_hw_init(void) 162 { 163 at91_periph_clk_enable(ATMEL_ID_PIODE); 164 165 at91_set_gpio_output(AT91_PIN_PD1, 0); 166 at91_set_gpio_output(AT91_PIN_PD3, 0); 167 } 168 #endif 169 170 #ifdef CONFIG_MACB 171 static void corvus_macb_hw_init(void) 172 { 173 /* Enable clock */ 174 at91_periph_clk_enable(ATMEL_ID_EMAC); 175 176 /* 177 * Disable pull-up on: 178 * RXDV (PA15) => PHY normal mode (not Test mode) 179 * ERX0 (PA12) => PHY ADDR0 180 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 181 * 182 * PHY has internal pull-down 183 */ 184 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 185 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); 186 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); 187 188 at91_phy_reset(); 189 190 /* Re-enable pull-up */ 191 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 192 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 193 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 194 195 /* And the pins. */ 196 at91_macb_hw_init(); 197 } 198 #endif 199 200 int board_early_init_f(void) 201 { 202 at91_seriald_hw_init(); 203 return 0; 204 } 205 206 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 207 /* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */ 208 void at91_udp_hw_init(void) 209 { 210 /* Enable UPLL clock */ 211 at91_upll_clk_enable(); 212 213 /* Enable UDPHS clock */ 214 at91_periph_clk_enable(ATMEL_ID_UDPHS); 215 } 216 #endif 217 218 int board_init(void) 219 { 220 /* address of boot parameters */ 221 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 222 223 #ifdef CONFIG_CMD_NAND 224 corvus_nand_hw_init(); 225 #endif 226 #ifdef CONFIG_ATMEL_SPI 227 at91_spi0_hw_init(1 << 4); 228 #endif 229 #ifdef CONFIG_HAS_DATAFLASH 230 at91_spi0_hw_init(1 << 0); 231 #endif 232 #ifdef CONFIG_MACB 233 corvus_macb_hw_init(); 234 #endif 235 #ifdef CONFIG_CMD_USB 236 taurus_usb_hw_init(); 237 #endif 238 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 239 at91_udp_hw_init(); 240 usba_udc_probe(&pdata); 241 #endif 242 return 0; 243 } 244 245 int dram_init(void) 246 { 247 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 248 CONFIG_SYS_SDRAM_SIZE); 249 return 0; 250 } 251 252 int board_eth_init(bd_t *bis) 253 { 254 int rc = 0; 255 #ifdef CONFIG_MACB 256 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 257 #endif 258 return rc; 259 } 260 261 /* SPI chip select control */ 262 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 263 { 264 return bus == 0 && cs < 2; 265 } 266 267 void spi_cs_activate(struct spi_slave *slave) 268 { 269 switch (slave->cs) { 270 case 1: 271 at91_set_gpio_output(AT91_PIN_PB18, 0); 272 break; 273 case 0: 274 default: 275 at91_set_gpio_output(AT91_PIN_PB3, 0); 276 break; 277 } 278 } 279 280 void spi_cs_deactivate(struct spi_slave *slave) 281 { 282 switch (slave->cs) { 283 case 1: 284 at91_set_gpio_output(AT91_PIN_PB18, 1); 285 break; 286 case 0: 287 default: 288 at91_set_gpio_output(AT91_PIN_PB3, 1); 289 break; 290 } 291 } 292