1 /* 2 * Board functions for Siemens CORVUS (AT91SAM9G45) based board 3 * (C) Copyright 2013 Siemens AG 4 * 5 * Based on: 6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 15 #include <common.h> 16 #include <asm/io.h> 17 #include <asm/arch/at91sam9g45_matrix.h> 18 #include <asm/arch/at91sam9_smc.h> 19 #include <asm/arch/at91_common.h> 20 #include <asm/arch/at91_pmc.h> 21 #include <asm/arch/at91_rstc.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/clk.h> 24 #include <lcd.h> 25 #include <atmel_lcdc.h> 26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 27 #include <net.h> 28 #endif 29 #include <netdev.h> 30 #include <spi.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 static void corvus_nand_hw_init(void) 35 { 36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 38 unsigned long csa; 39 40 /* Enable CS3 */ 41 csa = readl(&matrix->ebicsa); 42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 43 writel(csa, &matrix->ebicsa); 44 45 /* Configure SMC CS3 for NAND/SmartMedia */ 46 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 47 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 48 &smc->cs[3].setup); 49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | 50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), 51 &smc->cs[3].pulse); 52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), 53 &smc->cs[3].cycle); 54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 55 AT91_SMC_MODE_EXNW_DISABLE | 56 #ifdef CONFIG_SYS_NAND_DBW_16 57 AT91_SMC_MODE_DBW_16 | 58 #else /* CONFIG_SYS_NAND_DBW_8 */ 59 AT91_SMC_MODE_DBW_8 | 60 #endif 61 AT91_SMC_MODE_TDF_CYCLE(3), 62 &smc->cs[3].mode); 63 64 at91_periph_clk_enable(ATMEL_ID_PIOC); 65 66 /* Enable NandFlash */ 67 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 68 } 69 70 #if defined(CONFIG_SPL_BUILD) 71 #include <spl.h> 72 #include <nand.h> 73 74 void at91_spl_board_init(void) 75 { 76 /* 77 * For on the sam9m10g45ek board, the chip wm9711 stay in the test 78 * mode, so it need do some action to exit mode. 79 */ 80 at91_set_gpio_output(AT91_PIN_PD7, 0); 81 at91_set_gpio_output(AT91_PIN_PD8, 0); 82 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); 83 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); 84 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 85 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 86 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 87 88 corvus_nand_hw_init(); 89 90 /* Configure recovery button PINs */ 91 at91_set_gpio_input(AT91_PIN_PB7, 1); 92 93 /* check if button is pressed */ 94 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { 95 u32 boot_device; 96 97 debug("Recovery button pressed\n"); 98 boot_device = spl_boot_device(); 99 switch (boot_device) { 100 #ifdef CONFIG_SPL_NAND_SUPPORT 101 case BOOT_DEVICE_NAND: 102 nand_init(); 103 spl_nand_erase_one(0, 0); 104 break; 105 #endif 106 } 107 } 108 } 109 110 #include <asm/arch/atmel_mpddrc.h> 111 static void ddr2_conf(struct atmel_mpddr *ddr2) 112 { 113 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 114 115 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 116 ATMEL_MPDDRC_CR_NR_ROW_14 | 117 ATMEL_MPDDRC_CR_DIC_DS | 118 ATMEL_MPDDRC_CR_DQMS_SHARED | 119 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 120 ddr2->rtr = 0x24b; 121 122 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 123 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 124 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 125 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ 126 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 127 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 128 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 129 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 130 131 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 132 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 133 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 134 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 135 136 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 137 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 138 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 139 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 140 } 141 142 void mem_init(void) 143 { 144 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 145 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; 146 struct atmel_mpddr ddr2; 147 unsigned long csa; 148 149 ddr2_conf(&ddr2); 150 151 /* enable DDR2 clock */ 152 writel(0x4, &pmc->scer); 153 154 /* Chip select 1 is for DDR2/SDRAM */ 155 csa = readl(&mat->ebicsa); 156 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; 157 csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; 158 writel(csa, &mat->ebicsa); 159 160 /* DDRAM2 Controller initialize */ 161 ddr2_init(ATMEL_BASE_CS6, &ddr2); 162 } 163 #endif 164 165 #ifdef CONFIG_CMD_USB 166 static void taurus_usb_hw_init(void) 167 { 168 at91_periph_clk_enable(ATMEL_ID_PIODE); 169 170 at91_set_gpio_output(AT91_PIN_PD1, 0); 171 at91_set_gpio_output(AT91_PIN_PD3, 0); 172 } 173 #endif 174 175 #ifdef CONFIG_MACB 176 static void corvus_macb_hw_init(void) 177 { 178 /* Enable clock */ 179 at91_periph_clk_enable(ATMEL_ID_EMAC); 180 181 /* 182 * Disable pull-up on: 183 * RXDV (PA15) => PHY normal mode (not Test mode) 184 * ERX0 (PA12) => PHY ADDR0 185 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 186 * 187 * PHY has internal pull-down 188 */ 189 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 190 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); 191 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); 192 193 at91_phy_reset(); 194 195 /* Re-enable pull-up */ 196 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 197 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 198 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 199 200 /* And the pins. */ 201 at91_macb_hw_init(); 202 } 203 #endif 204 205 int board_early_init_f(void) 206 { 207 at91_seriald_hw_init(); 208 return 0; 209 } 210 211 int board_init(void) 212 { 213 /* address of boot parameters */ 214 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 215 216 #ifdef CONFIG_CMD_NAND 217 corvus_nand_hw_init(); 218 #endif 219 #ifdef CONFIG_ATMEL_SPI 220 at91_spi0_hw_init(1 << 4); 221 #endif 222 #ifdef CONFIG_HAS_DATAFLASH 223 at91_spi0_hw_init(1 << 0); 224 #endif 225 #ifdef CONFIG_MACB 226 corvus_macb_hw_init(); 227 #endif 228 #ifdef CONFIG_CMD_USB 229 taurus_usb_hw_init(); 230 #endif 231 return 0; 232 } 233 234 int dram_init(void) 235 { 236 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 237 CONFIG_SYS_SDRAM_SIZE); 238 return 0; 239 } 240 241 int board_eth_init(bd_t *bis) 242 { 243 int rc = 0; 244 #ifdef CONFIG_MACB 245 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 246 #endif 247 return rc; 248 } 249 250 /* SPI chip select control */ 251 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 252 { 253 return bus == 0 && cs < 2; 254 } 255 256 void spi_cs_activate(struct spi_slave *slave) 257 { 258 switch (slave->cs) { 259 case 1: 260 at91_set_gpio_output(AT91_PIN_PB18, 0); 261 break; 262 case 0: 263 default: 264 at91_set_gpio_output(AT91_PIN_PB3, 0); 265 break; 266 } 267 } 268 269 void spi_cs_deactivate(struct spi_slave *slave) 270 { 271 switch (slave->cs) { 272 case 1: 273 at91_set_gpio_output(AT91_PIN_PB18, 1); 274 break; 275 case 0: 276 default: 277 at91_set_gpio_output(AT91_PIN_PB3, 1); 278 break; 279 } 280 } 281