1 /* 2 * Board functions for Siemens CORVUS (AT91SAM9G45) based board 3 * (C) Copyright 2013 Siemens AG 4 * 5 * Based on: 6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 15 #include <common.h> 16 #include <asm/io.h> 17 #include <asm/arch/at91sam9g45_matrix.h> 18 #include <asm/arch/at91sam9_smc.h> 19 #include <asm/arch/at91_common.h> 20 #include <asm/arch/at91_pmc.h> 21 #include <asm/arch/at91_rstc.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/clk.h> 24 #include <lcd.h> 25 #include <atmel_lcdc.h> 26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 27 #include <net.h> 28 #endif 29 #include <netdev.h> 30 #include <spi.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 static void corvus_nand_hw_init(void) 35 { 36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 38 unsigned long csa; 39 40 /* Enable CS3 */ 41 csa = readl(&matrix->ebicsa); 42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 43 writel(csa, &matrix->ebicsa); 44 45 /* Configure SMC CS3 for NAND/SmartMedia */ 46 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 47 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 48 &smc->cs[3].setup); 49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | 50 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), 51 &smc->cs[3].pulse); 52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 53 &smc->cs[3].cycle); 54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 55 AT91_SMC_MODE_EXNW_DISABLE | 56 #ifdef CONFIG_SYS_NAND_DBW_16 57 AT91_SMC_MODE_DBW_16 | 58 #else /* CONFIG_SYS_NAND_DBW_8 */ 59 AT91_SMC_MODE_DBW_8 | 60 #endif 61 AT91_SMC_MODE_TDF_CYCLE(3), 62 &smc->cs[3].mode); 63 64 at91_periph_clk_enable(ATMEL_ID_PIOC); 65 at91_periph_clk_enable(ATMEL_ID_PIOA); 66 67 /* Enable NandFlash */ 68 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 70 } 71 72 #if defined(CONFIG_SPL_BUILD) 73 #include <spl.h> 74 #include <nand.h> 75 76 void at91_spl_board_init(void) 77 { 78 /* 79 * For on the sam9m10g45ek board, the chip wm9711 stay in the test 80 * mode, so it need do some action to exit mode. 81 */ 82 at91_set_gpio_output(AT91_PIN_PD7, 0); 83 at91_set_gpio_output(AT91_PIN_PD8, 0); 84 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); 85 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); 86 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 87 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 88 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 89 90 corvus_nand_hw_init(); 91 92 /* Configure recovery button PINs */ 93 at91_set_gpio_input(AT91_PIN_PB7, 1); 94 95 /* check if button is pressed */ 96 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { 97 u32 boot_device; 98 99 debug("Recovery button pressed\n"); 100 boot_device = spl_boot_device(); 101 switch (boot_device) { 102 #ifdef CONFIG_SPL_NAND_SUPPORT 103 case BOOT_DEVICE_NAND: 104 nand_init(); 105 spl_nand_erase_one(0, 0); 106 break; 107 #endif 108 } 109 } 110 } 111 112 #include <asm/arch/atmel_mpddrc.h> 113 static void ddr2_conf(struct atmel_mpddr *ddr2) 114 { 115 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 116 117 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 118 ATMEL_MPDDRC_CR_NR_ROW_14 | 119 ATMEL_MPDDRC_CR_DIC_DS | 120 ATMEL_MPDDRC_CR_DQMS_SHARED | 121 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 122 ddr2->rtr = 0x24b; 123 124 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 125 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 126 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 127 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ 128 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 129 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 130 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 131 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 132 133 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 134 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 135 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 136 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 137 138 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 139 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 140 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 141 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 142 } 143 144 void mem_init(void) 145 { 146 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 147 struct atmel_mpddr ddr2; 148 149 ddr2_conf(&ddr2); 150 151 /* enable DDR2 clock */ 152 writel(AT91_PMC_DDR, &pmc->scer); 153 154 /* DDRAM2 Controller initialize */ 155 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); 156 } 157 #endif 158 159 #ifdef CONFIG_CMD_USB 160 static void taurus_usb_hw_init(void) 161 { 162 at91_periph_clk_enable(ATMEL_ID_PIODE); 163 164 at91_set_gpio_output(AT91_PIN_PD1, 0); 165 at91_set_gpio_output(AT91_PIN_PD3, 0); 166 } 167 #endif 168 169 #ifdef CONFIG_MACB 170 static void corvus_macb_hw_init(void) 171 { 172 /* Enable clock */ 173 at91_periph_clk_enable(ATMEL_ID_EMAC); 174 175 /* 176 * Disable pull-up on: 177 * RXDV (PA15) => PHY normal mode (not Test mode) 178 * ERX0 (PA12) => PHY ADDR0 179 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 180 * 181 * PHY has internal pull-down 182 */ 183 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 184 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); 185 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); 186 187 at91_phy_reset(); 188 189 /* Re-enable pull-up */ 190 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 191 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 192 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 193 194 /* And the pins. */ 195 at91_macb_hw_init(); 196 } 197 #endif 198 199 int board_early_init_f(void) 200 { 201 at91_seriald_hw_init(); 202 return 0; 203 } 204 205 int board_init(void) 206 { 207 /* address of boot parameters */ 208 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 209 210 #ifdef CONFIG_CMD_NAND 211 corvus_nand_hw_init(); 212 #endif 213 #ifdef CONFIG_ATMEL_SPI 214 at91_spi0_hw_init(1 << 4); 215 #endif 216 #ifdef CONFIG_HAS_DATAFLASH 217 at91_spi0_hw_init(1 << 0); 218 #endif 219 #ifdef CONFIG_MACB 220 corvus_macb_hw_init(); 221 #endif 222 #ifdef CONFIG_CMD_USB 223 taurus_usb_hw_init(); 224 #endif 225 return 0; 226 } 227 228 int dram_init(void) 229 { 230 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 231 CONFIG_SYS_SDRAM_SIZE); 232 return 0; 233 } 234 235 int board_eth_init(bd_t *bis) 236 { 237 int rc = 0; 238 #ifdef CONFIG_MACB 239 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 240 #endif 241 return rc; 242 } 243 244 /* SPI chip select control */ 245 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 246 { 247 return bus == 0 && cs < 2; 248 } 249 250 void spi_cs_activate(struct spi_slave *slave) 251 { 252 switch (slave->cs) { 253 case 1: 254 at91_set_gpio_output(AT91_PIN_PB18, 0); 255 break; 256 case 0: 257 default: 258 at91_set_gpio_output(AT91_PIN_PB3, 0); 259 break; 260 } 261 } 262 263 void spi_cs_deactivate(struct spi_slave *slave) 264 { 265 switch (slave->cs) { 266 case 1: 267 at91_set_gpio_output(AT91_PIN_PB18, 1); 268 break; 269 case 0: 270 default: 271 at91_set_gpio_output(AT91_PIN_PB3, 1); 272 break; 273 } 274 } 275