1 /*
2  * SchulerControl GmbH, SC_SPS_1 module
3  *
4  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 #include <common.h>
27 #include <asm/gpio.h>
28 #include <asm/io.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/iomux-mx28.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/sys_proto.h>
33 #include <linux/mii.h>
34 #include <miiphy.h>
35 #include <netdev.h>
36 #include <errno.h>
37 
38 DECLARE_GLOBAL_DATA_PTR;
39 
40 /*
41  * Functions
42  */
43 int board_early_init_f(void)
44 {
45 	/* IO0 clock at 480MHz */
46 	mx28_set_ioclk(MXC_IOCLK0, 480000);
47 	/* IO1 clock at 480MHz */
48 	mx28_set_ioclk(MXC_IOCLK1, 480000);
49 
50 	/* SSP0 clock at 96MHz */
51 	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
52 	/* SSP2 clock at 96MHz */
53 	mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
54 
55 #ifdef	CONFIG_CMD_USB
56 	mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
57 	mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 |
58 			MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
59 	gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1);
60 #endif
61 
62 	return 0;
63 }
64 
65 int board_init(void)
66 {
67 	/* Adress of boot parameters */
68 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
69 
70 	return 0;
71 }
72 
73 int dram_init(void)
74 {
75 	return mx28_dram_init();
76 }
77 
78 #ifdef	CONFIG_CMD_MMC
79 int board_mmc_init(bd_t *bis)
80 {
81 	return mxsmmc_initialize(bis, 0, NULL);
82 }
83 #endif
84 
85 #ifdef	CONFIG_CMD_NET
86 int board_eth_init(bd_t *bis)
87 {
88 	struct mx28_clkctrl_regs *clkctrl_regs =
89 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
90 	int ret;
91 
92 	ret = cpu_eth_init(bis);
93 
94 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
95 		CLKCTRL_ENET_TIME_SEL_MASK,
96 		CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN);
97 
98 	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
99 	if (ret) {
100 		printf("FEC MXS: Unable to init FEC0\n");
101 		return ret;
102 	}
103 
104 	ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
105 	if (ret) {
106 		printf("FEC MXS: Unable to init FEC1\n");
107 		return ret;
108 	}
109 
110 	return ret;
111 }
112 
113 #endif
114