1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> 4 * Copyright 2007 Embedded Specialties, Inc. 5 * Joe Hamman joe.hamman@embeddedspecialties.com 6 * 7 * Copyright 2004 Freescale Semiconductor. 8 * Jeff Brown 9 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 10 * 11 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 12 */ 13 14 #include <common.h> 15 #include <command.h> 16 #include <pci.h> 17 #include <asm/processor.h> 18 #include <asm/immap_86xx.h> 19 #include <asm/fsl_pci.h> 20 #include <fsl_ddr_sdram.h> 21 #include <asm/fsl_serdes.h> 22 #include <linux/libfdt.h> 23 #include <fdt_support.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 long int fixed_sdram (void); 28 29 int board_early_init_f (void) 30 { 31 return 0; 32 } 33 34 int checkboard (void) 35 { 36 puts ("Board: Wind River SBC8641D\n"); 37 38 return 0; 39 } 40 41 int dram_init(void) 42 { 43 long dram_size = 0; 44 45 #if defined(CONFIG_SPD_EEPROM) 46 dram_size = fsl_ddr_sdram(); 47 #else 48 dram_size = fixed_sdram (); 49 #endif 50 51 debug (" DDR: "); 52 gd->ram_size = dram_size; 53 54 return 0; 55 } 56 57 #if defined(CONFIG_SYS_DRAM_TEST) 58 int testdram (void) 59 { 60 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 61 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 62 uint *p; 63 64 puts ("SDRAM test phase 1:\n"); 65 for (p = pstart; p < pend; p++) 66 *p = 0xaaaaaaaa; 67 68 for (p = pstart; p < pend; p++) { 69 if (*p != 0xaaaaaaaa) { 70 printf ("SDRAM test fails at: %08x\n", (uint) p); 71 return 1; 72 } 73 } 74 75 puts ("SDRAM test phase 2:\n"); 76 for (p = pstart; p < pend; p++) 77 *p = 0x55555555; 78 79 for (p = pstart; p < pend; p++) { 80 if (*p != 0x55555555) { 81 printf ("SDRAM test fails at: %08x\n", (uint) p); 82 return 1; 83 } 84 } 85 86 puts ("SDRAM test passed.\n"); 87 return 0; 88 } 89 #endif 90 91 #if !defined(CONFIG_SPD_EEPROM) 92 /* 93 * Fixed sdram init -- doesn't use serial presence detect. 94 */ 95 long int fixed_sdram (void) 96 { 97 #if !defined(CONFIG_SYS_RAMBOOT) 98 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 99 volatile struct ccsr_ddr *ddr = &immap->im_ddr1; 100 101 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 102 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; 103 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; 104 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; 105 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 106 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; 107 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; 108 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; 109 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 110 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 111 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 112 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 113 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A; 114 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; 115 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 116 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 117 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL; 118 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 119 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 120 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 121 122 asm ("sync;isync"); 123 124 udelay (500); 125 126 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B; 127 asm ("sync; isync"); 128 129 udelay (500); 130 ddr = &immap->im_ddr2; 131 132 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS; 133 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS; 134 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS; 135 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS; 136 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG; 137 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG; 138 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG; 139 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG; 140 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH; 141 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; 142 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; 143 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; 144 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A; 145 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; 146 ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; 147 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; 148 ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL; 149 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; 150 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT; 151 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL; 152 153 asm ("sync;isync"); 154 155 udelay (500); 156 157 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B; 158 asm ("sync; isync"); 159 160 udelay (500); 161 #endif 162 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 163 } 164 #endif /* !defined(CONFIG_SPD_EEPROM) */ 165 166 #if defined(CONFIG_PCI) 167 /* 168 * Initialize PCI Devices, report devices found. 169 */ 170 171 void pci_init_board(void) 172 { 173 fsl_pcie_init_board(0); 174 } 175 #endif /* CONFIG_PCI */ 176 177 178 #if defined(CONFIG_OF_BOARD_SETUP) 179 int ft_board_setup(void *blob, bd_t *bd) 180 { 181 ft_cpu_setup(blob, bd); 182 183 FT_FSL_PCI_SETUP; 184 185 return 0; 186 } 187 #endif 188 189 void sbc8641d_reset_board (void) 190 { 191 puts ("Resetting board....\n"); 192 } 193 194 /* 195 * get_board_sys_clk 196 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ 197 */ 198 199 unsigned long get_board_sys_clk (ulong dummy) 200 { 201 int i; 202 ulong val = 0; 203 204 i = 5; 205 i &= 0x07; 206 207 switch (i) { 208 case 0: 209 val = 33000000; 210 break; 211 case 1: 212 val = 40000000; 213 break; 214 case 2: 215 val = 50000000; 216 break; 217 case 3: 218 val = 66000000; 219 break; 220 case 4: 221 val = 83000000; 222 break; 223 case 5: 224 val = 100000000; 225 break; 226 case 6: 227 val = 134000000; 228 break; 229 case 7: 230 val = 166000000; 231 break; 232 } 233 234 return val; 235 } 236 237 void board_reset(void) 238 { 239 #ifdef CONFIG_SYS_RESET_ADDRESS 240 ulong addr = CONFIG_SYS_RESET_ADDRESS; 241 242 /* flush and disable I/D cache */ 243 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); 244 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); 245 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); 246 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); 247 __asm__ __volatile__ ("sync"); 248 __asm__ __volatile__ ("mtspr 1008, 4"); 249 __asm__ __volatile__ ("isync"); 250 __asm__ __volatile__ ("sync"); 251 __asm__ __volatile__ ("mtspr 1008, 5"); 252 __asm__ __volatile__ ("isync"); 253 __asm__ __volatile__ ("sync"); 254 255 /* 256 * SRR0 has system reset vector, SRR1 has default MSR value 257 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value 258 */ 259 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); 260 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); 261 __asm__ __volatile__ ("mtspr 27, 4"); 262 __asm__ __volatile__ ("rfi"); 263 #endif 264 } 265