1 /* 2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman joe.hamman@embeddedspecialties.com 5 * 6 * Copyright 2004 Freescale Semiconductor. 7 * Jeff Brown 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #include <common.h> 32 #include <command.h> 33 #include <pci.h> 34 #include <asm/processor.h> 35 #include <asm/immap_86xx.h> 36 #include <asm/immap_fsl_pci.h> 37 #include <asm/fsl_ddr_sdram.h> 38 #include <libfdt.h> 39 #include <fdt_support.h> 40 41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 42 extern void ddr_enable_ecc (unsigned int dram_size); 43 #endif 44 45 long int fixed_sdram (void); 46 47 int board_early_init_f (void) 48 { 49 return 0; 50 } 51 52 int checkboard (void) 53 { 54 puts ("Board: Wind River SBC8641D\n"); 55 56 return 0; 57 } 58 59 phys_size_t initdram (int board_type) 60 { 61 long dram_size = 0; 62 63 #if defined(CONFIG_SPD_EEPROM) 64 dram_size = fsl_ddr_sdram(); 65 #else 66 dram_size = fixed_sdram (); 67 #endif 68 69 #if defined(CONFIG_SYS_RAMBOOT) 70 puts (" DDR: "); 71 return dram_size; 72 #endif 73 74 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 75 /* 76 * Initialize and enable DDR ECC. 77 */ 78 ddr_enable_ecc (dram_size); 79 #endif 80 81 puts (" DDR: "); 82 return dram_size; 83 } 84 85 #if defined(CONFIG_SYS_DRAM_TEST) 86 int testdram (void) 87 { 88 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 89 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 90 uint *p; 91 92 puts ("SDRAM test phase 1:\n"); 93 for (p = pstart; p < pend; p++) 94 *p = 0xaaaaaaaa; 95 96 for (p = pstart; p < pend; p++) { 97 if (*p != 0xaaaaaaaa) { 98 printf ("SDRAM test fails at: %08x\n", (uint) p); 99 return 1; 100 } 101 } 102 103 puts ("SDRAM test phase 2:\n"); 104 for (p = pstart; p < pend; p++) 105 *p = 0x55555555; 106 107 for (p = pstart; p < pend; p++) { 108 if (*p != 0x55555555) { 109 printf ("SDRAM test fails at: %08x\n", (uint) p); 110 return 1; 111 } 112 } 113 114 puts ("SDRAM test passed.\n"); 115 return 0; 116 } 117 #endif 118 119 #if !defined(CONFIG_SPD_EEPROM) 120 /* 121 * Fixed sdram init -- doesn't use serial presence detect. 122 */ 123 long int fixed_sdram (void) 124 { 125 #if !defined(CONFIG_SYS_RAMBOOT) 126 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 127 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 128 129 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 130 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; 131 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; 132 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; 133 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 134 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; 135 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; 136 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; 137 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 138 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 139 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 140 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 141 ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A; 142 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; 143 ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; 144 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 145 ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; 146 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 147 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 148 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 149 150 asm ("sync;isync"); 151 152 udelay (500); 153 154 ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B; 155 asm ("sync; isync"); 156 157 udelay (500); 158 ddr = &immap->im_ddr2; 159 160 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS; 161 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS; 162 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS; 163 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS; 164 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG; 165 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG; 166 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG; 167 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG; 168 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH; 169 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; 170 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; 171 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; 172 ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A; 173 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; 174 ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1; 175 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; 176 ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; 177 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; 178 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT; 179 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL; 180 181 asm ("sync;isync"); 182 183 udelay (500); 184 185 ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B; 186 asm ("sync; isync"); 187 188 udelay (500); 189 #endif 190 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 191 } 192 #endif /* !defined(CONFIG_SPD_EEPROM) */ 193 194 #if defined(CONFIG_PCI) 195 /* 196 * Initialize PCI Devices, report devices found. 197 */ 198 199 #ifndef CONFIG_PCI_PNP 200 static struct pci_config_table pci_fsl86xxads_config_table[] = { 201 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 202 PCI_IDSEL_NUMBER, PCI_ANY_ID, 203 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 204 PCI_ENET0_MEMADDR, 205 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, 206 {} 207 }; 208 #endif 209 210 static struct pci_controller pci1_hose = { 211 #ifndef CONFIG_PCI_PNP 212 config_table:pci_mpc86xxcts_config_table 213 #endif 214 }; 215 #endif /* CONFIG_PCI */ 216 217 #ifdef CONFIG_PCI2 218 static struct pci_controller pci2_hose; 219 #endif /* CONFIG_PCI2 */ 220 221 int first_free_busno = 0; 222 223 void pci_init_board(void) 224 { 225 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 226 volatile ccsr_gur_t *gur = &immap->im_gur; 227 uint devdisr = gur->devdisr; 228 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) 229 >> MPC8641_PORDEVSR_IO_SEL_SHIFT; 230 231 #ifdef CONFIG_PCI1 232 { 233 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 234 extern void fsl_pci_init(struct pci_controller *hose); 235 struct pci_controller *hose = &pci1_hose; 236 #ifdef DEBUG 237 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) 238 >> MPC8641_PORBMSR_HA_SHIFT; 239 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 240 #endif 241 if ((io_sel == 2 || io_sel == 3 || io_sel == 5 242 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) 243 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 244 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 245 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 246 if (pci->pme_msg_det) { 247 pci->pme_msg_det = 0xffffffff; 248 debug(" with errors. Clearing. Now 0x%08x", 249 pci->pme_msg_det); 250 } 251 debug("\n"); 252 253 /* inbound */ 254 pci_set_region(hose->regions + 0, 255 CONFIG_SYS_PCI_MEMORY_BUS, 256 CONFIG_SYS_PCI_MEMORY_PHYS, 257 CONFIG_SYS_PCI_MEMORY_SIZE, 258 PCI_REGION_MEM | PCI_REGION_MEMORY); 259 260 /* outbound memory */ 261 pci_set_region(hose->regions + 1, 262 CONFIG_SYS_PCI1_MEM_BASE, 263 CONFIG_SYS_PCI1_MEM_PHYS, 264 CONFIG_SYS_PCI1_MEM_SIZE, 265 PCI_REGION_MEM); 266 267 /* outbound io */ 268 pci_set_region(hose->regions + 2, 269 CONFIG_SYS_PCI1_IO_BASE, 270 CONFIG_SYS_PCI1_IO_PHYS, 271 CONFIG_SYS_PCI1_IO_SIZE, 272 PCI_REGION_IO); 273 274 hose->region_count = 3; 275 276 hose->first_busno=first_free_busno; 277 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 278 279 fsl_pci_init(hose); 280 281 first_free_busno=hose->last_busno+1; 282 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 283 hose->first_busno,hose->last_busno); 284 285 } else { 286 puts("PCI-EXPRESS 1: Disabled\n"); 287 } 288 } 289 #else 290 puts("PCI-EXPRESS1: Disabled\n"); 291 #endif /* CONFIG_PCI1 */ 292 293 #ifdef CONFIG_PCI2 294 { 295 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; 296 extern void fsl_pci_init(struct pci_controller *hose); 297 struct pci_controller *hose = &pci2_hose; 298 299 300 /* inbound */ 301 pci_set_region(hose->regions + 0, 302 CONFIG_SYS_PCI_MEMORY_BUS, 303 CONFIG_SYS_PCI_MEMORY_PHYS, 304 CONFIG_SYS_PCI_MEMORY_SIZE, 305 PCI_REGION_MEM | PCI_REGION_MEMORY); 306 307 /* outbound memory */ 308 pci_set_region(hose->regions + 1, 309 CONFIG_SYS_PCI2_MEM_BASE, 310 CONFIG_SYS_PCI2_MEM_PHYS, 311 CONFIG_SYS_PCI2_MEM_SIZE, 312 PCI_REGION_MEM); 313 314 /* outbound io */ 315 pci_set_region(hose->regions + 2, 316 CONFIG_SYS_PCI2_IO_BASE, 317 CONFIG_SYS_PCI2_IO_PHYS, 318 CONFIG_SYS_PCI2_IO_SIZE, 319 PCI_REGION_IO); 320 321 hose->region_count = 3; 322 323 hose->first_busno=first_free_busno; 324 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 325 326 fsl_pci_init(hose); 327 328 first_free_busno=hose->last_busno+1; 329 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 330 hose->first_busno,hose->last_busno); 331 } 332 #else 333 puts("PCI-EXPRESS 2: Disabled\n"); 334 #endif /* CONFIG_PCI2 */ 335 336 } 337 338 339 #if defined(CONFIG_OF_BOARD_SETUP) 340 341 void 342 ft_board_setup (void *blob, bd_t *bd) 343 { 344 int node, tmp[2]; 345 const char *path; 346 347 ft_cpu_setup(blob, bd); 348 349 node = fdt_path_offset(blob, "/aliases"); 350 tmp[0] = 0; 351 if (node >= 0) { 352 #ifdef CONFIG_PCI1 353 path = fdt_getprop(blob, node, "pci0", NULL); 354 if (path) { 355 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 356 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 357 } 358 #endif 359 #ifdef CONFIG_PCI2 360 path = fdt_getprop(blob, node, "pci1", NULL); 361 if (path) { 362 tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; 363 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 364 } 365 #endif 366 } 367 } 368 #endif 369 370 void sbc8641d_reset_board (void) 371 { 372 puts ("Resetting board....\n"); 373 } 374 375 /* 376 * get_board_sys_clk 377 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ 378 */ 379 380 unsigned long get_board_sys_clk (ulong dummy) 381 { 382 int i; 383 ulong val = 0; 384 385 i = 5; 386 i &= 0x07; 387 388 switch (i) { 389 case 0: 390 val = 33000000; 391 break; 392 case 1: 393 val = 40000000; 394 break; 395 case 2: 396 val = 50000000; 397 break; 398 case 3: 399 val = 66000000; 400 break; 401 case 4: 402 val = 83000000; 403 break; 404 case 5: 405 val = 100000000; 406 break; 407 case 6: 408 val = 134000000; 409 break; 410 case 7: 411 val = 166000000; 412 break; 413 } 414 415 return val; 416 } 417