1 /* 2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman joe.hamman@embeddedspecialties.com 5 * 6 * Copyright 2004 Freescale Semiconductor. 7 * Jeff Brown 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #include <common.h> 32 #include <command.h> 33 #include <pci.h> 34 #include <asm/processor.h> 35 #include <asm/immap_86xx.h> 36 #include <asm/fsl_pci.h> 37 #include <asm/fsl_ddr_sdram.h> 38 #include <libfdt.h> 39 #include <fdt_support.h> 40 41 long int fixed_sdram (void); 42 43 int board_early_init_f (void) 44 { 45 return 0; 46 } 47 48 int checkboard (void) 49 { 50 puts ("Board: Wind River SBC8641D\n"); 51 52 return 0; 53 } 54 55 phys_size_t initdram (int board_type) 56 { 57 long dram_size = 0; 58 59 #if defined(CONFIG_SPD_EEPROM) 60 dram_size = fsl_ddr_sdram(); 61 #else 62 dram_size = fixed_sdram (); 63 #endif 64 65 #if defined(CONFIG_SYS_RAMBOOT) 66 puts (" DDR: "); 67 return dram_size; 68 #endif 69 70 puts (" DDR: "); 71 return dram_size; 72 } 73 74 #if defined(CONFIG_SYS_DRAM_TEST) 75 int testdram (void) 76 { 77 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 78 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 79 uint *p; 80 81 puts ("SDRAM test phase 1:\n"); 82 for (p = pstart; p < pend; p++) 83 *p = 0xaaaaaaaa; 84 85 for (p = pstart; p < pend; p++) { 86 if (*p != 0xaaaaaaaa) { 87 printf ("SDRAM test fails at: %08x\n", (uint) p); 88 return 1; 89 } 90 } 91 92 puts ("SDRAM test phase 2:\n"); 93 for (p = pstart; p < pend; p++) 94 *p = 0x55555555; 95 96 for (p = pstart; p < pend; p++) { 97 if (*p != 0x55555555) { 98 printf ("SDRAM test fails at: %08x\n", (uint) p); 99 return 1; 100 } 101 } 102 103 puts ("SDRAM test passed.\n"); 104 return 0; 105 } 106 #endif 107 108 #if !defined(CONFIG_SPD_EEPROM) 109 /* 110 * Fixed sdram init -- doesn't use serial presence detect. 111 */ 112 long int fixed_sdram (void) 113 { 114 #if !defined(CONFIG_SYS_RAMBOOT) 115 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 116 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 117 118 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 119 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; 120 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; 121 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; 122 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 123 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; 124 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; 125 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; 126 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 127 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 128 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 129 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 130 ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A; 131 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; 132 ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; 133 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 134 ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; 135 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 136 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 137 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 138 139 asm ("sync;isync"); 140 141 udelay (500); 142 143 ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B; 144 asm ("sync; isync"); 145 146 udelay (500); 147 ddr = &immap->im_ddr2; 148 149 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS; 150 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS; 151 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS; 152 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS; 153 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG; 154 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG; 155 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG; 156 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG; 157 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH; 158 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; 159 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; 160 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; 161 ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A; 162 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; 163 ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1; 164 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; 165 ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; 166 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; 167 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT; 168 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL; 169 170 asm ("sync;isync"); 171 172 udelay (500); 173 174 ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B; 175 asm ("sync; isync"); 176 177 udelay (500); 178 #endif 179 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 180 } 181 #endif /* !defined(CONFIG_SPD_EEPROM) */ 182 183 #if defined(CONFIG_PCI) 184 /* 185 * Initialize PCI Devices, report devices found. 186 */ 187 188 #ifndef CONFIG_PCI_PNP 189 static struct pci_config_table pci_fsl86xxads_config_table[] = { 190 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 191 PCI_IDSEL_NUMBER, PCI_ANY_ID, 192 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 193 PCI_ENET0_MEMADDR, 194 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, 195 {} 196 }; 197 #endif 198 199 static struct pci_controller pci1_hose = { 200 #ifndef CONFIG_PCI_PNP 201 config_table:pci_mpc86xxcts_config_table 202 #endif 203 }; 204 #endif /* CONFIG_PCI */ 205 206 #ifdef CONFIG_PCI2 207 static struct pci_controller pci2_hose; 208 #endif /* CONFIG_PCI2 */ 209 210 int first_free_busno = 0; 211 212 void pci_init_board(void) 213 { 214 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 215 volatile ccsr_gur_t *gur = &immap->im_gur; 216 uint devdisr = gur->devdisr; 217 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) 218 >> MPC8641_PORDEVSR_IO_SEL_SHIFT; 219 220 #ifdef CONFIG_PCI1 221 { 222 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 223 struct pci_controller *hose = &pci1_hose; 224 struct pci_region *r = hose->regions; 225 #ifdef DEBUG 226 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) 227 >> MPC8641_PORBMSR_HA_SHIFT; 228 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 229 #endif 230 if ((io_sel == 2 || io_sel == 3 || io_sel == 5 231 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) 232 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 233 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 234 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 235 if (pci->pme_msg_det) { 236 pci->pme_msg_det = 0xffffffff; 237 debug(" with errors. Clearing. Now 0x%08x", 238 pci->pme_msg_det); 239 } 240 debug("\n"); 241 242 /* inbound */ 243 r += fsl_pci_setup_inbound_windows(r); 244 245 /* outbound memory */ 246 pci_set_region(r++, 247 CONFIG_SYS_PCI1_MEM_BUS, 248 CONFIG_SYS_PCI1_MEM_PHYS, 249 CONFIG_SYS_PCI1_MEM_SIZE, 250 PCI_REGION_MEM); 251 252 /* outbound io */ 253 pci_set_region(r++, 254 CONFIG_SYS_PCI1_IO_BUS, 255 CONFIG_SYS_PCI1_IO_PHYS, 256 CONFIG_SYS_PCI1_IO_SIZE, 257 PCI_REGION_IO); 258 259 hose->region_count = r - hose->regions; 260 261 hose->first_busno=first_free_busno; 262 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 263 264 fsl_pci_init(hose); 265 266 first_free_busno=hose->last_busno+1; 267 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 268 hose->first_busno,hose->last_busno); 269 270 } else { 271 puts("PCI-EXPRESS 1: Disabled\n"); 272 } 273 } 274 #else 275 puts("PCI-EXPRESS1: Disabled\n"); 276 #endif /* CONFIG_PCI1 */ 277 278 #ifdef CONFIG_PCI2 279 { 280 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; 281 struct pci_controller *hose = &pci2_hose; 282 struct pci_region *r = hose->regions; 283 284 285 /* inbound */ 286 r += fsl_pci_setup_inbound_windows(r); 287 288 /* outbound memory */ 289 pci_set_region(r++, 290 CONFIG_SYS_PCI2_MEM_BUS, 291 CONFIG_SYS_PCI2_MEM_PHYS, 292 CONFIG_SYS_PCI2_MEM_SIZE, 293 PCI_REGION_MEM); 294 295 /* outbound io */ 296 pci_set_region(r++, 297 CONFIG_SYS_PCI2_IO_BUS, 298 CONFIG_SYS_PCI2_IO_PHYS, 299 CONFIG_SYS_PCI2_IO_SIZE, 300 PCI_REGION_IO); 301 302 hose->region_count = r - hose->regions; 303 304 hose->first_busno=first_free_busno; 305 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 306 307 fsl_pci_init(hose); 308 309 first_free_busno=hose->last_busno+1; 310 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 311 hose->first_busno,hose->last_busno); 312 } 313 #else 314 puts("PCI-EXPRESS 2: Disabled\n"); 315 #endif /* CONFIG_PCI2 */ 316 317 } 318 319 320 #if defined(CONFIG_OF_BOARD_SETUP) 321 void ft_board_setup (void *blob, bd_t *bd) 322 { 323 ft_cpu_setup(blob, bd); 324 325 #ifdef CONFIG_PCI1 326 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 327 #endif 328 #ifdef CONFIG_PCI2 329 ft_fsl_pci_setup(blob, "pci1", &pci2_hose); 330 #endif 331 } 332 #endif 333 334 void sbc8641d_reset_board (void) 335 { 336 puts ("Resetting board....\n"); 337 } 338 339 /* 340 * get_board_sys_clk 341 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ 342 */ 343 344 unsigned long get_board_sys_clk (ulong dummy) 345 { 346 int i; 347 ulong val = 0; 348 349 i = 5; 350 i &= 0x07; 351 352 switch (i) { 353 case 0: 354 val = 33000000; 355 break; 356 case 1: 357 val = 40000000; 358 break; 359 case 2: 360 val = 50000000; 361 break; 362 case 3: 363 val = 66000000; 364 break; 365 case 4: 366 val = 83000000; 367 break; 368 case 5: 369 val = 100000000; 370 break; 371 case 6: 372 val = 134000000; 373 break; 374 case 7: 375 val = 166000000; 376 break; 377 } 378 379 return val; 380 } 381 382 void board_reset(void) 383 { 384 #ifdef CONFIG_SYS_RESET_ADDRESS 385 ulong addr = CONFIG_SYS_RESET_ADDRESS; 386 387 /* flush and disable I/D cache */ 388 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); 389 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); 390 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); 391 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); 392 __asm__ __volatile__ ("sync"); 393 __asm__ __volatile__ ("mtspr 1008, 4"); 394 __asm__ __volatile__ ("isync"); 395 __asm__ __volatile__ ("sync"); 396 __asm__ __volatile__ ("mtspr 1008, 5"); 397 __asm__ __volatile__ ("isync"); 398 __asm__ __volatile__ ("sync"); 399 400 /* 401 * SRR0 has system reset vector, SRR1 has default MSR value 402 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value 403 */ 404 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); 405 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); 406 __asm__ __volatile__ ("mtspr 27, 4"); 407 __asm__ __volatile__ ("rfi"); 408 #endif 409 } 410 411 #ifdef CONFIG_MP 412 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 413 414 void board_lmb_reserve(struct lmb *lmb) 415 { 416 cpu_mp_lmb_reserve(lmb); 417 } 418 #endif 419