1 /* 2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman joe.hamman@embeddedspecialties.com 5 * 6 * Copyright 2004 Freescale Semiconductor. 7 * Jeff Brown 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #include <common.h> 32 #include <command.h> 33 #include <pci.h> 34 #include <asm/processor.h> 35 #include <asm/immap_86xx.h> 36 #include <asm/immap_fsl_pci.h> 37 #include <spd.h> 38 39 #if defined(CONFIG_OF_FLAT_TREE) 40 #include <ft_build.h> 41 extern void ft_cpu_setup (void *blob, bd_t * bd); 42 #endif 43 44 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 45 extern void ddr_enable_ecc (unsigned int dram_size); 46 #endif 47 48 #if defined(CONFIG_SPD_EEPROM) 49 #include "spd_sdram.h" 50 #endif 51 52 void sdram_init (void); 53 long int fixed_sdram (void); 54 55 int board_early_init_f (void) 56 { 57 return 0; 58 } 59 60 int checkboard (void) 61 { 62 puts ("Board: Wind River SBC8641D\n"); 63 64 return 0; 65 } 66 67 long int initdram (int board_type) 68 { 69 long dram_size = 0; 70 71 #if defined(CONFIG_SPD_EEPROM) 72 dram_size = spd_sdram (); 73 #else 74 dram_size = fixed_sdram (); 75 #endif 76 77 #if defined(CFG_RAMBOOT) 78 puts (" DDR: "); 79 return dram_size; 80 #endif 81 82 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 83 /* 84 * Initialize and enable DDR ECC. 85 */ 86 ddr_enable_ecc (dram_size); 87 #endif 88 89 puts (" DDR: "); 90 return dram_size; 91 } 92 93 #if defined(CFG_DRAM_TEST) 94 int testdram (void) 95 { 96 uint *pstart = (uint *) CFG_MEMTEST_START; 97 uint *pend = (uint *) CFG_MEMTEST_END; 98 uint *p; 99 100 puts ("SDRAM test phase 1:\n"); 101 for (p = pstart; p < pend; p++) 102 *p = 0xaaaaaaaa; 103 104 for (p = pstart; p < pend; p++) { 105 if (*p != 0xaaaaaaaa) { 106 printf ("SDRAM test fails at: %08x\n", (uint) p); 107 return 1; 108 } 109 } 110 111 puts ("SDRAM test phase 2:\n"); 112 for (p = pstart; p < pend; p++) 113 *p = 0x55555555; 114 115 for (p = pstart; p < pend; p++) { 116 if (*p != 0x55555555) { 117 printf ("SDRAM test fails at: %08x\n", (uint) p); 118 return 1; 119 } 120 } 121 122 puts ("SDRAM test passed.\n"); 123 return 0; 124 } 125 #endif 126 127 #if !defined(CONFIG_SPD_EEPROM) 128 /* 129 * Fixed sdram init -- doesn't use serial presence detect. 130 */ 131 long int fixed_sdram (void) 132 { 133 #if !defined(CFG_RAMBOOT) 134 volatile immap_t *immap = (immap_t *) CFG_IMMR; 135 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 136 137 ddr->cs0_bnds = CFG_DDR_CS0_BNDS; 138 ddr->cs1_bnds = CFG_DDR_CS1_BNDS; 139 ddr->cs2_bnds = CFG_DDR_CS2_BNDS; 140 ddr->cs3_bnds = CFG_DDR_CS3_BNDS; 141 ddr->cs0_config = CFG_DDR_CS0_CONFIG; 142 ddr->cs1_config = CFG_DDR_CS1_CONFIG; 143 ddr->cs2_config = CFG_DDR_CS2_CONFIG; 144 ddr->cs3_config = CFG_DDR_CS3_CONFIG; 145 ddr->ext_refrec = CFG_DDR_EXT_REFRESH; 146 ddr->timing_cfg_0 = CFG_DDR_TIMING_0; 147 ddr->timing_cfg_1 = CFG_DDR_TIMING_1; 148 ddr->timing_cfg_2 = CFG_DDR_TIMING_2; 149 ddr->sdram_cfg_1 = CFG_DDR_CFG_1A; 150 ddr->sdram_cfg_2 = CFG_DDR_CFG_2; 151 ddr->sdram_mode_1 = CFG_DDR_MODE_1; 152 ddr->sdram_mode_2 = CFG_DDR_MODE_2; 153 ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL; 154 ddr->sdram_interval = CFG_DDR_INTERVAL; 155 ddr->sdram_data_init = CFG_DDR_DATA_INIT; 156 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; 157 158 asm ("sync;isync"); 159 160 udelay (500); 161 162 ddr->sdram_cfg_1 = CFG_DDR_CFG_1B; 163 asm ("sync; isync"); 164 165 udelay (500); 166 ddr = &immap->im_ddr2; 167 168 ddr->cs0_bnds = CFG_DDR2_CS0_BNDS; 169 ddr->cs1_bnds = CFG_DDR2_CS1_BNDS; 170 ddr->cs2_bnds = CFG_DDR2_CS2_BNDS; 171 ddr->cs3_bnds = CFG_DDR2_CS3_BNDS; 172 ddr->cs0_config = CFG_DDR2_CS0_CONFIG; 173 ddr->cs1_config = CFG_DDR2_CS1_CONFIG; 174 ddr->cs2_config = CFG_DDR2_CS2_CONFIG; 175 ddr->cs3_config = CFG_DDR2_CS3_CONFIG; 176 ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; 177 ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; 178 ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; 179 ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; 180 ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A; 181 ddr->sdram_cfg_2 = CFG_DDR2_CFG_2; 182 ddr->sdram_mode_1 = CFG_DDR2_MODE_1; 183 ddr->sdram_mode_2 = CFG_DDR2_MODE_2; 184 ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL; 185 ddr->sdram_interval = CFG_DDR2_INTERVAL; 186 ddr->sdram_data_init = CFG_DDR2_DATA_INIT; 187 ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL; 188 189 asm ("sync;isync"); 190 191 udelay (500); 192 193 ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B; 194 asm ("sync; isync"); 195 196 udelay (500); 197 #endif 198 return CFG_SDRAM_SIZE * 1024 * 1024; 199 } 200 #endif /* !defined(CONFIG_SPD_EEPROM) */ 201 202 #if defined(CONFIG_PCI) 203 /* 204 * Initialize PCI Devices, report devices found. 205 */ 206 207 #ifndef CONFIG_PCI_PNP 208 static struct pci_config_table pci_fsl86xxads_config_table[] = { 209 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 210 PCI_IDSEL_NUMBER, PCI_ANY_ID, 211 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 212 PCI_ENET0_MEMADDR, 213 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, 214 {} 215 }; 216 #endif 217 218 static struct pci_controller pci1_hose = { 219 #ifndef CONFIG_PCI_PNP 220 config_table:pci_mpc86xxcts_config_table 221 #endif 222 }; 223 #endif /* CONFIG_PCI */ 224 225 #ifdef CONFIG_PCI2 226 static struct pci_controller pci2_hose; 227 #endif /* CONFIG_PCI2 */ 228 229 int first_free_busno = 0; 230 231 void pci_init_board(void) 232 { 233 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 234 volatile ccsr_gur_t *gur = &immap->im_gur; 235 uint devdisr = gur->devdisr; 236 uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; 237 238 #ifdef CONFIG_PCI1 239 { 240 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 241 extern void fsl_pci_init(struct pci_controller *hose); 242 struct pci_controller *hose = &pci1_hose; 243 #ifdef DEBUG 244 uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; 245 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 246 #endif 247 if ((io_sel == 2 || io_sel == 3 || io_sel == 5 248 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) 249 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 250 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 251 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 252 if (pci->pme_msg_det) { 253 pci->pme_msg_det = 0xffffffff; 254 debug(" with errors. Clearing. Now 0x%08x", 255 pci->pme_msg_det); 256 } 257 debug("\n"); 258 259 /* inbound */ 260 pci_set_region(hose->regions + 0, 261 CFG_PCI_MEMORY_BUS, 262 CFG_PCI_MEMORY_PHYS, 263 CFG_PCI_MEMORY_SIZE, 264 PCI_REGION_MEM | PCI_REGION_MEMORY); 265 266 /* outbound memory */ 267 pci_set_region(hose->regions + 1, 268 CFG_PCI1_MEM_BASE, 269 CFG_PCI1_MEM_PHYS, 270 CFG_PCI1_MEM_SIZE, 271 PCI_REGION_MEM); 272 273 /* outbound io */ 274 pci_set_region(hose->regions + 2, 275 CFG_PCI1_IO_BASE, 276 CFG_PCI1_IO_PHYS, 277 CFG_PCI1_IO_SIZE, 278 PCI_REGION_IO); 279 280 hose->region_count = 3; 281 282 hose->first_busno=first_free_busno; 283 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 284 285 fsl_pci_init(hose); 286 287 first_free_busno=hose->last_busno+1; 288 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 289 hose->first_busno,hose->last_busno); 290 291 } else { 292 puts("PCI-EXPRESS 1: Disabled\n"); 293 } 294 } 295 #else 296 puts("PCI-EXPRESS1: Disabled\n"); 297 #endif /* CONFIG_PCI1 */ 298 299 #ifdef CONFIG_PCI2 300 { 301 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; 302 extern void fsl_pci_init(struct pci_controller *hose); 303 struct pci_controller *hose = &pci2_hose; 304 305 306 /* inbound */ 307 pci_set_region(hose->regions + 0, 308 CFG_PCI_MEMORY_BUS, 309 CFG_PCI_MEMORY_PHYS, 310 CFG_PCI_MEMORY_SIZE, 311 PCI_REGION_MEM | PCI_REGION_MEMORY); 312 313 /* outbound memory */ 314 pci_set_region(hose->regions + 1, 315 CFG_PCI2_MEM_BASE, 316 CFG_PCI2_MEM_PHYS, 317 CFG_PCI2_MEM_SIZE, 318 PCI_REGION_MEM); 319 320 /* outbound io */ 321 pci_set_region(hose->regions + 2, 322 CFG_PCI2_IO_BASE, 323 CFG_PCI2_IO_PHYS, 324 CFG_PCI2_IO_SIZE, 325 PCI_REGION_IO); 326 327 hose->region_count = 3; 328 329 hose->first_busno=first_free_busno; 330 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 331 332 fsl_pci_init(hose); 333 334 first_free_busno=hose->last_busno+1; 335 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 336 hose->first_busno,hose->last_busno); 337 } 338 #else 339 puts("PCI-EXPRESS 2: Disabled\n"); 340 #endif /* CONFIG_PCI2 */ 341 342 } 343 344 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) 345 void ft_board_setup (void *blob, bd_t * bd) 346 { 347 u32 *p; 348 int len; 349 350 ft_cpu_setup (blob, bd); 351 352 p = ft_get_prop (blob, "/memory/reg", &len); 353 if (p != NULL) { 354 *p++ = cpu_to_be32 (bd->bi_memstart); 355 *p = cpu_to_be32 (bd->bi_memsize); 356 } 357 } 358 #endif 359 360 void sbc8641d_reset_board (void) 361 { 362 puts ("Resetting board....\n"); 363 } 364 365 /* 366 * get_board_sys_clk 367 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ 368 */ 369 370 unsigned long get_board_sys_clk (ulong dummy) 371 { 372 int i; 373 ulong val = 0; 374 375 i = 5; 376 i &= 0x07; 377 378 switch (i) { 379 case 0: 380 val = 33000000; 381 break; 382 case 1: 383 val = 40000000; 384 break; 385 case 2: 386 val = 50000000; 387 break; 388 case 3: 389 val = 66000000; 390 break; 391 case 4: 392 val = 83000000; 393 break; 394 case 5: 395 val = 100000000; 396 break; 397 case 6: 398 val = 134000000; 399 break; 400 case 7: 401 val = 166000000; 402 break; 403 } 404 405 return val; 406 } 407