1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/mmu.h> 28 29 struct fsl_e_tlb_entry tlb_table[] = { 30 /* TLB 0 - for temp stack in cache */ 31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 32 MAS3_SX|MAS3_SW|MAS3_SR, 0, 33 0, 0, BOOKE_PAGESZ_4K, 0), 34 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 35 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 36 MAS3_SX|MAS3_SW|MAS3_SR, 0, 37 0, 0, BOOKE_PAGESZ_4K, 0), 38 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 39 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 40 MAS3_SX|MAS3_SW|MAS3_SR, 0, 41 0, 0, BOOKE_PAGESZ_4K, 0), 42 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 43 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44 MAS3_SX|MAS3_SW|MAS3_SR, 0, 45 0, 0, BOOKE_PAGESZ_4K, 0), 46 47 /* 48 * TLB 0: 16M Non-cacheable, guarded 49 * 0xff800000 16M TLB for 8MB FLASH 50 * Out of reset this entry is only 4K. 51 */ 52 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, 53 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54 0, 0, BOOKE_PAGESZ_16M, 1), 55 56 /* 57 * TLB 1: 256M Non-cacheable, guarded 58 * 0x80000000 256M PCI1 MEM First half 59 */ 60 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, 61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 0, 1, BOOKE_PAGESZ_256M, 1), 63 64 /* 65 * TLB 2: 256M Non-cacheable, guarded 66 * 0x90000000 256M PCI1 MEM Second half 67 */ 68 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, 69 CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, 70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71 0, 2, BOOKE_PAGESZ_256M, 1), 72 73 /* 74 * TLB 3: 256M Cacheable, non-guarded 75 * 0x0 256M DDR SDRAM 76 */ 77 #if !defined(CONFIG_SPD_EEPROM) 78 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 79 MAS3_SX|MAS3_SW|MAS3_SR, 0, 80 0, 3, BOOKE_PAGESZ_256M, 1), 81 #endif 82 83 /* 84 * TLB 4: 64M Non-cacheable, guarded 85 * 0xe0000000 1M CCSRBAR 86 * 0xe2000000 16M PCI1 IO 87 */ 88 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 89 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 90 0, 4, BOOKE_PAGESZ_64M, 1), 91 92 /* 93 * TLB 5: 64M Cacheable, non-guarded 94 * 0xf0000000 64M LBC SDRAM 95 */ 96 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, 97 MAS3_SX|MAS3_SW|MAS3_SR, 0, 98 0, 5, BOOKE_PAGESZ_64M, 1), 99 100 /* 101 * TLB 6: 16M Cacheable, non-guarded 102 * 0xf8000000 1M 7-segment LED display 103 * 0xf8100000 1M User switches 104 * 0xf8300000 1M Board revision 105 * 0xf8b00000 1M EEPROM 106 */ 107 SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, 108 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 109 0, 6, BOOKE_PAGESZ_16M, 1), 110 }; 111 112 int num_tlb_entries = ARRAY_SIZE(tlb_table); 113