1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/mmu.h> 12 13 struct fsl_e_tlb_entry tlb_table[] = { 14 /* TLB 0 - for temp stack in cache */ 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 0, 0, BOOKE_PAGESZ_4K, 0), 22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 0, 0, BOOKE_PAGESZ_4K, 0), 26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28 MAS3_SX|MAS3_SW|MAS3_SR, 0, 29 0, 0, BOOKE_PAGESZ_4K, 0), 30 31 /* 32 * TLB 0: 64M Non-cacheable, guarded 33 * 0xfc000000 56M unused 34 * 0xff800000 8M boot FLASH 35 * .... or .... 36 * 0xfc000000 64M user flash 37 * 38 * Out of reset this entry is only 4K. 39 */ 40 SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, 41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42 0, 0, BOOKE_PAGESZ_64M, 1), 43 44 /* 45 * TLB 1: 1G Non-cacheable, guarded 46 * 0x80000000 512M PCI1 MEM 47 * 0xa0000000 512M PCIe MEM 48 */ 49 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, 50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51 0, 1, BOOKE_PAGESZ_1G, 1), 52 53 /* 54 * TLB 2: 64M Non-cacheable, guarded 55 * 0xe0000000 1M CCSRBAR 56 * 0xe2000000 8M PCI1 IO 57 * 0xe2800000 8M PCIe IO 58 */ 59 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 60 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61 0, 2, BOOKE_PAGESZ_64M, 1), 62 63 #ifdef CONFIG_SYS_LBC_SDRAM_BASE 64 /* 65 * TLB 3: 64M Cacheable, non-guarded 66 * 0xf0000000 64M LBC SDRAM First half 67 */ 68 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, 69 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 70 0, 3, BOOKE_PAGESZ_64M, 1), 71 72 /* 73 * TLB 4: 64M Cacheable, non-guarded 74 * 0xf4000000 64M LBC SDRAM Second half 75 */ 76 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, 77 CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, 78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 79 0, 4, BOOKE_PAGESZ_64M, 1), 80 #endif 81 82 /* 83 * TLB 5: 16M Cacheable, non-guarded 84 * 0xf8000000 1M 7-segment LED display 85 * 0xf8100000 1M User switches 86 * 0xf8300000 1M Board revision 87 * 0xf8b00000 1M EEPROM 88 */ 89 SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, 90 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 91 0, 5, BOOKE_PAGESZ_16M, 1), 92 93 #ifndef CONFIG_SYS_ALT_BOOT 94 /* 95 * TLB 6: 64M Non-cacheable, guarded 96 * 0xec000000 64M 64MB user FLASH 97 */ 98 SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, 99 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100 0, 6, BOOKE_PAGESZ_64M, 1), 101 #else 102 /* 103 * TLB 6: 4M Non-cacheable, guarded 104 * 0xef800000 4M 1st 1/2 8MB soldered FLASH 105 */ 106 SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, 107 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 108 0, 6, BOOKE_PAGESZ_4M, 1), 109 110 /* 111 * TLB 7: 4M Non-cacheable, guarded 112 * 0xefc00000 4M 2nd half 8MB soldered FLASH 113 */ 114 SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, 115 CONFIG_SYS_ALT_FLASH + 0x400000, 116 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 117 0, 7, BOOKE_PAGESZ_4M, 1), 118 #endif 119 120 }; 121 122 int num_tlb_entries = ARRAY_SIZE(tlb_table); 123