1 /* 2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> 3 * 4 * Copyright 2007 Embedded Specialties, Inc. 5 * 6 * Copyright 2004, 2007 Freescale Semiconductor. 7 * 8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <pci.h> 31 #include <asm/processor.h> 32 #include <asm/immap_85xx.h> 33 #include <asm/fsl_pci.h> 34 #include <asm/fsl_ddr_sdram.h> 35 #include <spd_sdram.h> 36 #include <netdev.h> 37 #include <tsec.h> 38 #include <miiphy.h> 39 #include <libfdt.h> 40 #include <fdt_support.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 void local_bus_init(void); 45 void sdram_init(void); 46 long int fixed_sdram (void); 47 48 int board_early_init_f (void) 49 { 50 return 0; 51 } 52 53 int checkboard (void) 54 { 55 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 56 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; 57 58 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 59 in_8(rev) >> 4); 60 61 /* 62 * Initialize local bus. 63 */ 64 local_bus_init (); 65 66 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ 67 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ 68 return 0; 69 } 70 71 phys_size_t 72 initdram(int board_type) 73 { 74 long dram_size = 0; 75 76 puts("Initializing\n"); 77 78 #if defined(CONFIG_DDR_DLL) 79 { 80 /* 81 * Work around to stabilize DDR DLL MSYNC_IN. 82 * Errata DDR9 seems to have been fixed. 83 * This is now the workaround for Errata DDR11: 84 * Override DLL = 1, Course Adj = 1, Tap Select = 0 85 */ 86 87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 88 89 out_be32(&gur->ddrdllcr, 0x81000000); 90 asm("sync;isync;msync"); 91 udelay(200); 92 } 93 #endif 94 95 #if defined(CONFIG_SPD_EEPROM) 96 dram_size = fsl_ddr_sdram(); 97 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 98 dram_size *= 0x100000; 99 #else 100 dram_size = fixed_sdram (); 101 #endif 102 103 /* 104 * SDRAM Initialization 105 */ 106 sdram_init(); 107 108 puts(" DDR: "); 109 return dram_size; 110 } 111 112 /* 113 * Initialize Local Bus 114 */ 115 void 116 local_bus_init(void) 117 { 118 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 119 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 120 121 uint clkdiv; 122 uint lbc_hz; 123 sys_info_t sysinfo; 124 125 get_sys_info(&sysinfo); 126 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; 127 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 128 129 out_be32(&gur->lbiuiplldcr1, 0x00078080); 130 if (clkdiv == 16) { 131 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 132 } else if (clkdiv == 8) { 133 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 134 } else if (clkdiv == 4) { 135 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 136 } 137 138 setbits_be32(&lbc->lcrr, 0x00030000); 139 140 asm("sync;isync;msync"); 141 142 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ 143 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ 144 } 145 146 /* 147 * Initialize SDRAM memory on the Local Bus. 148 */ 149 void 150 sdram_init(void) 151 { 152 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) 153 154 uint idx; 155 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 156 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 157 uint lsdmr_common; 158 159 puts(" SDRAM: "); 160 161 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 162 163 /* 164 * Setup SDRAM Base and Option Registers 165 */ 166 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); 167 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); 168 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); 169 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); 170 171 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); 172 asm("msync"); 173 174 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); 175 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); 176 asm("msync"); 177 178 /* 179 * MPC8548 uses "new" 15-16 style addressing. 180 */ 181 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 182 lsdmr_common |= LSDMR_BSMA1516; 183 184 /* 185 * Issue PRECHARGE ALL command. 186 */ 187 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); 188 asm("sync;msync"); 189 *sdram_addr = 0xff; 190 ppcDcbf((unsigned long) sdram_addr); 191 udelay(100); 192 193 /* 194 * Issue 8 AUTO REFRESH commands. 195 */ 196 for (idx = 0; idx < 8; idx++) { 197 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); 198 asm("sync;msync"); 199 *sdram_addr = 0xff; 200 ppcDcbf((unsigned long) sdram_addr); 201 udelay(100); 202 } 203 204 /* 205 * Issue 8 MODE-set command. 206 */ 207 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); 208 asm("sync;msync"); 209 *sdram_addr = 0xff; 210 ppcDcbf((unsigned long) sdram_addr); 211 udelay(100); 212 213 /* 214 * Issue NORMAL OP command. 215 */ 216 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); 217 asm("sync;msync"); 218 *sdram_addr = 0xff; 219 ppcDcbf((unsigned long) sdram_addr); 220 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 221 222 #endif /* enable SDRAM init */ 223 } 224 225 #if defined(CONFIG_SYS_DRAM_TEST) 226 int 227 testdram(void) 228 { 229 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 230 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 231 uint *p; 232 233 printf("Testing DRAM from 0x%08x to 0x%08x\n", 234 CONFIG_SYS_MEMTEST_START, 235 CONFIG_SYS_MEMTEST_END); 236 237 printf("DRAM test phase 1:\n"); 238 for (p = pstart; p < pend; p++) 239 *p = 0xaaaaaaaa; 240 241 for (p = pstart; p < pend; p++) { 242 if (*p != 0xaaaaaaaa) { 243 printf ("DRAM test fails at: %08x\n", (uint) p); 244 return 1; 245 } 246 } 247 248 printf("DRAM test phase 2:\n"); 249 for (p = pstart; p < pend; p++) 250 *p = 0x55555555; 251 252 for (p = pstart; p < pend; p++) { 253 if (*p != 0x55555555) { 254 printf ("DRAM test fails at: %08x\n", (uint) p); 255 return 1; 256 } 257 } 258 259 printf("DRAM test passed.\n"); 260 return 0; 261 } 262 #endif 263 264 #if !defined(CONFIG_SPD_EEPROM) 265 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 266 /************************************************************************* 267 * fixed_sdram init -- doesn't use serial presence detect. 268 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 269 ************************************************************************/ 270 long int fixed_sdram (void) 271 { 272 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); 273 274 out_be32(&ddr->cs0_bnds, 0x0000007f); 275 out_be32(&ddr->cs1_bnds, 0x008000ff); 276 out_be32(&ddr->cs2_bnds, 0x00000000); 277 out_be32(&ddr->cs3_bnds, 0x00000000); 278 out_be32(&ddr->cs0_config, 0x80010101); 279 out_be32(&ddr->cs1_config, 0x80010101); 280 out_be32(&ddr->cs2_config, 0x00000000); 281 out_be32(&ddr->cs3_config, 0x00000000); 282 out_be32(&ddr->timing_cfg_3, 0x00000000); 283 out_be32(&ddr->timing_cfg_0, 0x00220802); 284 out_be32(&ddr->timing_cfg_1, 0x38377322); 285 out_be32(&ddr->timing_cfg_2, 0x0fa044C7); 286 out_be32(&ddr->sdram_cfg, 0x4300C000); 287 out_be32(&ddr->sdram_cfg_2, 0x24401000); 288 out_be32(&ddr->sdram_mode, 0x23C00542); 289 out_be32(&ddr->sdram_mode_2, 0x00000000); 290 out_be32(&ddr->sdram_interval, 0x05080100); 291 out_be32(&ddr->sdram_md_cntl, 0x00000000); 292 out_be32(&ddr->sdram_data_init, 0x00000000); 293 out_be32(&ddr->sdram_clk_cntl, 0x03800000); 294 asm("sync;isync;msync"); 295 udelay(500); 296 297 #if defined (CONFIG_DDR_ECC) 298 /* Enable ECC checking */ 299 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); 300 #else 301 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 302 #endif 303 304 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 305 } 306 #endif 307 308 #ifdef CONFIG_PCI1 309 static struct pci_controller pci1_hose; 310 #endif /* CONFIG_PCI1 */ 311 312 #ifdef CONFIG_PCIE1 313 static struct pci_controller pcie1_hose; 314 #endif /* CONFIG_PCIE1 */ 315 316 317 #ifdef CONFIG_PCI 318 void 319 pci_init_board(void) 320 { 321 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 322 struct fsl_pci_info pci_info[2]; 323 u32 devdisr, pordevsr, porpllsr, io_sel; 324 int first_free_busno = 0; 325 int num = 0; 326 327 #ifdef CONFIG_PCIE1 328 int pcie_configured; 329 #endif 330 331 devdisr = in_be32(&gur->devdisr); 332 pordevsr = in_be32(&gur->pordevsr); 333 porpllsr = in_be32(&gur->porpllsr); 334 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 335 336 debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 337 338 #ifdef CONFIG_PCI1 339 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 340 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; 341 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 342 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 343 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ 344 345 printf (" PCI host: %d bit, %s MHz, %s, %s\n", 346 (pci_32) ? 32 : 64, 347 (pci_speed == 33000000) ? "33" : 348 (pci_speed == 66000000) ? "66" : "unknown", 349 pci_clk_sel ? "sync" : "async", 350 pci_arb ? "arbiter" : "external-arbiter"); 351 352 SET_STD_PCI_INFO(pci_info[num], 1); 353 first_free_busno = fsl_pci_init_port(&pci_info[num++], 354 &pci1_hose, first_free_busno); 355 } else { 356 printf (" PCI: disabled\n"); 357 } 358 359 puts("\n"); 360 #else 361 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 362 #endif 363 364 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ 365 366 #ifdef CONFIG_PCIE1 367 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 368 369 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 370 SET_STD_PCIE_INFO(pci_info[num], 1); 371 printf (" PCIE at base address %lx\n", pci_info[num].regs); 372 first_free_busno = fsl_pci_init_port(&pci_info[num++], 373 &pcie1_hose, first_free_busno); 374 } else { 375 printf (" PCIE: disabled\n"); 376 } 377 378 puts("\n"); 379 #else 380 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 381 #endif 382 } 383 #endif 384 385 int board_eth_init(bd_t *bis) 386 { 387 tsec_standard_init(bis); 388 pci_eth_init(bis); 389 return 0; /* otherwise cpu_eth_init gets run */ 390 } 391 392 int last_stage_init(void) 393 { 394 return 0; 395 } 396 397 #if defined(CONFIG_OF_BOARD_SETUP) 398 void ft_board_setup(void *blob, bd_t *bd) 399 { 400 ft_cpu_setup(blob, bd); 401 402 #ifdef CONFIG_FSL_PCI_INIT 403 FT_FSL_PCI_SETUP; 404 #endif 405 } 406 #endif 407