1 /* 2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> 3 * 4 * Copyright 2007 Embedded Specialties, Inc. 5 * 6 * Copyright 2004, 2007 Freescale Semiconductor. 7 * 8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <pci.h> 15 #include <asm/processor.h> 16 #include <asm/immap_85xx.h> 17 #include <asm/fsl_pci.h> 18 #include <fsl_ddr_sdram.h> 19 #include <asm/fsl_serdes.h> 20 #include <spd_sdram.h> 21 #include <netdev.h> 22 #include <tsec.h> 23 #include <miiphy.h> 24 #include <libfdt.h> 25 #include <fdt_support.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 void local_bus_init(void); 30 31 int board_early_init_f (void) 32 { 33 return 0; 34 } 35 36 int checkboard (void) 37 { 38 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 39 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; 40 41 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 42 in_8(rev) >> 4); 43 44 /* 45 * Initialize local bus. 46 */ 47 local_bus_init (); 48 49 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ 50 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ 51 return 0; 52 } 53 54 /* 55 * Initialize Local Bus 56 */ 57 void 58 local_bus_init(void) 59 { 60 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 61 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 62 63 uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR; 64 sys_info_t sysinfo; 65 66 get_sys_info(&sysinfo); 67 68 lbc_mhz = sysinfo.freq_localbus / 1000000; 69 clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus; 70 71 debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz); 72 73 out_be32(&gur->lbiuiplldcr1, 0x00078080); 74 if (clkdiv == 16) { 75 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 76 } else if (clkdiv == 8) { 77 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 78 } else if (clkdiv == 4) { 79 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 80 } 81 82 /* 83 * Local Bus Clock > 83.3 MHz. According to timing 84 * specifications set LCRR[EADC] to 2 delay cycles. 85 */ 86 if (lbc_mhz > 83) { 87 lcrr &= ~LCRR_EADC; 88 lcrr |= LCRR_EADC_2; 89 } 90 91 /* 92 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 93 * disable PLL bypass for Local Bus Clock > 83 MHz. 94 */ 95 if (lbc_mhz >= 66) 96 lcrr &= (~LCRR_DBYP); /* DLL Enabled */ 97 98 else 99 lcrr |= LCRR_DBYP; /* DLL Bypass */ 100 101 out_be32(&lbc->lcrr, lcrr); 102 asm("sync;isync;msync"); 103 104 /* 105 * According to MPC8548ERMAD Rev.1.3 read back LCRR 106 * and terminate with isync 107 */ 108 lcrr = in_be32(&lbc->lcrr); 109 asm ("isync;"); 110 111 /* let DLL stabilize */ 112 udelay(500); 113 114 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ 115 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ 116 } 117 118 /* 119 * Initialize SDRAM memory on the Local Bus. 120 */ 121 void lbc_sdram_init(void) 122 { 123 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) 124 125 uint idx; 126 const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; 127 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 128 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 129 uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2); 130 131 puts(" SDRAM: "); 132 133 print_size(size, "\n"); 134 135 /* 136 * Setup SDRAM Base and Option Registers 137 */ 138 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); 139 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); 140 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); 141 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); 142 143 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); 144 asm("msync"); 145 146 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); 147 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); 148 asm("msync"); 149 150 /* 151 * Issue PRECHARGE ALL command. 152 */ 153 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL); 154 asm("sync;msync"); 155 *sdram_addr = 0xff; 156 ppcDcbf((unsigned long) sdram_addr); 157 *sdram_addr2 = 0xff; 158 ppcDcbf((unsigned long) sdram_addr2); 159 udelay(100); 160 161 /* 162 * Issue 8 AUTO REFRESH commands. 163 */ 164 for (idx = 0; idx < 8; idx++) { 165 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH); 166 asm("sync;msync"); 167 *sdram_addr = 0xff; 168 ppcDcbf((unsigned long) sdram_addr); 169 *sdram_addr2 = 0xff; 170 ppcDcbf((unsigned long) sdram_addr2); 171 udelay(100); 172 } 173 174 /* 175 * Issue 8 MODE-set command. 176 */ 177 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW); 178 asm("sync;msync"); 179 *sdram_addr = 0xff; 180 ppcDcbf((unsigned long) sdram_addr); 181 *sdram_addr2 = 0xff; 182 ppcDcbf((unsigned long) sdram_addr2); 183 udelay(100); 184 185 /* 186 * Issue RFEN command. 187 */ 188 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN); 189 asm("sync;msync"); 190 *sdram_addr = 0xff; 191 ppcDcbf((unsigned long) sdram_addr); 192 *sdram_addr2 = 0xff; 193 ppcDcbf((unsigned long) sdram_addr2); 194 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 195 196 #endif /* enable SDRAM init */ 197 } 198 199 #if defined(CONFIG_SYS_DRAM_TEST) 200 int 201 testdram(void) 202 { 203 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 204 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 205 uint *p; 206 207 printf("Testing DRAM from 0x%08x to 0x%08x\n", 208 CONFIG_SYS_MEMTEST_START, 209 CONFIG_SYS_MEMTEST_END); 210 211 printf("DRAM test phase 1:\n"); 212 for (p = pstart; p < pend; p++) 213 *p = 0xaaaaaaaa; 214 215 for (p = pstart; p < pend; p++) { 216 if (*p != 0xaaaaaaaa) { 217 printf ("DRAM test fails at: %08x\n", (uint) p); 218 return 1; 219 } 220 } 221 222 printf("DRAM test phase 2:\n"); 223 for (p = pstart; p < pend; p++) 224 *p = 0x55555555; 225 226 for (p = pstart; p < pend; p++) { 227 if (*p != 0x55555555) { 228 printf ("DRAM test fails at: %08x\n", (uint) p); 229 return 1; 230 } 231 } 232 233 printf("DRAM test passed.\n"); 234 return 0; 235 } 236 #endif 237 238 #ifdef CONFIG_PCI1 239 static struct pci_controller pci1_hose; 240 #endif /* CONFIG_PCI1 */ 241 242 #ifdef CONFIG_PCI 243 void 244 pci_init_board(void) 245 { 246 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 247 int first_free_busno = 0; 248 249 #ifdef CONFIG_PCI1 250 struct fsl_pci_info pci_info; 251 u32 devdisr = in_be32(&gur->devdisr); 252 u32 pordevsr = in_be32(&gur->pordevsr); 253 u32 porpllsr = in_be32(&gur->porpllsr); 254 255 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 256 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; 257 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 258 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 259 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ 260 261 printf("PCI: Host, %d bit, %s MHz, %s, %s\n", 262 (pci_32) ? 32 : 64, 263 (pci_speed == 33000000) ? "33" : 264 (pci_speed == 66000000) ? "66" : "unknown", 265 pci_clk_sel ? "sync" : "async", 266 pci_arb ? "arbiter" : "external-arbiter"); 267 268 SET_STD_PCI_INFO(pci_info, 1); 269 set_next_law(pci_info.mem_phys, 270 law_size_bits(pci_info.mem_size), pci_info.law); 271 set_next_law(pci_info.io_phys, 272 law_size_bits(pci_info.io_size), pci_info.law); 273 274 first_free_busno = fsl_pci_init_port(&pci_info, 275 &pci1_hose, first_free_busno); 276 } else { 277 printf("PCI: disabled\n"); 278 } 279 280 puts("\n"); 281 #else 282 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 283 #endif 284 285 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ 286 287 fsl_pcie_init_board(first_free_busno); 288 } 289 #endif 290 291 int board_eth_init(bd_t *bis) 292 { 293 tsec_standard_init(bis); 294 pci_eth_init(bis); 295 return 0; /* otherwise cpu_eth_init gets run */ 296 } 297 298 int last_stage_init(void) 299 { 300 return 0; 301 } 302 303 #if defined(CONFIG_OF_BOARD_SETUP) 304 int ft_board_setup(void *blob, bd_t *bd) 305 { 306 ft_cpu_setup(blob, bd); 307 308 #ifdef CONFIG_FSL_PCI_INIT 309 FT_FSL_PCI_SETUP; 310 #endif 311 312 return 0; 313 } 314 #endif 315