1 /* 2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> 3 * 4 * Copyright 2007 Embedded Specialties, Inc. 5 * 6 * Copyright 2004, 2007 Freescale Semiconductor. 7 * 8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <pci.h> 31 #include <asm/processor.h> 32 #include <asm/immap_85xx.h> 33 #include <asm/fsl_pci.h> 34 #include <asm/fsl_ddr_sdram.h> 35 #include <asm/fsl_serdes.h> 36 #include <spd_sdram.h> 37 #include <netdev.h> 38 #include <tsec.h> 39 #include <miiphy.h> 40 #include <libfdt.h> 41 #include <fdt_support.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 void local_bus_init(void); 46 47 int board_early_init_f (void) 48 { 49 return 0; 50 } 51 52 int checkboard (void) 53 { 54 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 55 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; 56 57 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 58 in_8(rev) >> 4); 59 60 /* 61 * Initialize local bus. 62 */ 63 local_bus_init (); 64 65 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ 66 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ 67 return 0; 68 } 69 70 /* 71 * Initialize Local Bus 72 */ 73 void 74 local_bus_init(void) 75 { 76 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 77 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 78 79 uint clkdiv; 80 sys_info_t sysinfo; 81 82 get_sys_info(&sysinfo); 83 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; 84 85 out_be32(&gur->lbiuiplldcr1, 0x00078080); 86 if (clkdiv == 16) { 87 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 88 } else if (clkdiv == 8) { 89 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 90 } else if (clkdiv == 4) { 91 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 92 } 93 94 setbits_be32(&lbc->lcrr, 0x00030000); 95 96 asm("sync;isync;msync"); 97 98 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ 99 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ 100 } 101 102 /* 103 * Initialize SDRAM memory on the Local Bus. 104 */ 105 void lbc_sdram_init(void) 106 { 107 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) 108 109 uint idx; 110 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 111 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 112 uint lsdmr_common; 113 114 puts(" SDRAM: "); 115 116 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 117 118 /* 119 * Setup SDRAM Base and Option Registers 120 */ 121 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); 122 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); 123 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); 124 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); 125 126 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); 127 asm("msync"); 128 129 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); 130 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); 131 asm("msync"); 132 133 /* 134 * MPC8548 uses "new" 15-16 style addressing. 135 */ 136 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 137 lsdmr_common |= LSDMR_BSMA1516; 138 139 /* 140 * Issue PRECHARGE ALL command. 141 */ 142 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); 143 asm("sync;msync"); 144 *sdram_addr = 0xff; 145 ppcDcbf((unsigned long) sdram_addr); 146 udelay(100); 147 148 /* 149 * Issue 8 AUTO REFRESH commands. 150 */ 151 for (idx = 0; idx < 8; idx++) { 152 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); 153 asm("sync;msync"); 154 *sdram_addr = 0xff; 155 ppcDcbf((unsigned long) sdram_addr); 156 udelay(100); 157 } 158 159 /* 160 * Issue 8 MODE-set command. 161 */ 162 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); 163 asm("sync;msync"); 164 *sdram_addr = 0xff; 165 ppcDcbf((unsigned long) sdram_addr); 166 udelay(100); 167 168 /* 169 * Issue NORMAL OP command. 170 */ 171 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); 172 asm("sync;msync"); 173 *sdram_addr = 0xff; 174 ppcDcbf((unsigned long) sdram_addr); 175 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 176 177 #endif /* enable SDRAM init */ 178 } 179 180 #if defined(CONFIG_SYS_DRAM_TEST) 181 int 182 testdram(void) 183 { 184 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 185 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 186 uint *p; 187 188 printf("Testing DRAM from 0x%08x to 0x%08x\n", 189 CONFIG_SYS_MEMTEST_START, 190 CONFIG_SYS_MEMTEST_END); 191 192 printf("DRAM test phase 1:\n"); 193 for (p = pstart; p < pend; p++) 194 *p = 0xaaaaaaaa; 195 196 for (p = pstart; p < pend; p++) { 197 if (*p != 0xaaaaaaaa) { 198 printf ("DRAM test fails at: %08x\n", (uint) p); 199 return 1; 200 } 201 } 202 203 printf("DRAM test phase 2:\n"); 204 for (p = pstart; p < pend; p++) 205 *p = 0x55555555; 206 207 for (p = pstart; p < pend; p++) { 208 if (*p != 0x55555555) { 209 printf ("DRAM test fails at: %08x\n", (uint) p); 210 return 1; 211 } 212 } 213 214 printf("DRAM test passed.\n"); 215 return 0; 216 } 217 #endif 218 219 #if !defined(CONFIG_SPD_EEPROM) 220 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 221 /************************************************************************* 222 * fixed_sdram init -- doesn't use serial presence detect. 223 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 224 ************************************************************************/ 225 phys_size_t fixed_sdram(void) 226 { 227 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); 228 229 out_be32(&ddr->cs0_bnds, 0x0000007f); 230 out_be32(&ddr->cs1_bnds, 0x008000ff); 231 out_be32(&ddr->cs2_bnds, 0x00000000); 232 out_be32(&ddr->cs3_bnds, 0x00000000); 233 out_be32(&ddr->cs0_config, 0x80010101); 234 out_be32(&ddr->cs1_config, 0x80010101); 235 out_be32(&ddr->cs2_config, 0x00000000); 236 out_be32(&ddr->cs3_config, 0x00000000); 237 out_be32(&ddr->timing_cfg_3, 0x00000000); 238 out_be32(&ddr->timing_cfg_0, 0x00220802); 239 out_be32(&ddr->timing_cfg_1, 0x38377322); 240 out_be32(&ddr->timing_cfg_2, 0x0fa044C7); 241 out_be32(&ddr->sdram_cfg, 0x4300C000); 242 out_be32(&ddr->sdram_cfg_2, 0x24401000); 243 out_be32(&ddr->sdram_mode, 0x23C00542); 244 out_be32(&ddr->sdram_mode_2, 0x00000000); 245 out_be32(&ddr->sdram_interval, 0x05080100); 246 out_be32(&ddr->sdram_md_cntl, 0x00000000); 247 out_be32(&ddr->sdram_data_init, 0x00000000); 248 out_be32(&ddr->sdram_clk_cntl, 0x03800000); 249 asm("sync;isync;msync"); 250 udelay(500); 251 252 #if defined (CONFIG_DDR_ECC) 253 /* Enable ECC checking */ 254 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); 255 #else 256 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 257 #endif 258 259 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 260 } 261 #endif 262 263 #ifdef CONFIG_PCI1 264 static struct pci_controller pci1_hose; 265 #endif /* CONFIG_PCI1 */ 266 267 #ifdef CONFIG_PCI 268 void 269 pci_init_board(void) 270 { 271 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 272 int first_free_busno = 0; 273 274 #ifdef CONFIG_PCI1 275 struct fsl_pci_info pci_info; 276 u32 devdisr = in_be32(&gur->devdisr); 277 u32 pordevsr = in_be32(&gur->pordevsr); 278 u32 porpllsr = in_be32(&gur->porpllsr); 279 280 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 281 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; 282 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 283 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 284 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ 285 286 printf("PCI: Host, %d bit, %s MHz, %s, %s\n", 287 (pci_32) ? 32 : 64, 288 (pci_speed == 33000000) ? "33" : 289 (pci_speed == 66000000) ? "66" : "unknown", 290 pci_clk_sel ? "sync" : "async", 291 pci_arb ? "arbiter" : "external-arbiter"); 292 293 SET_STD_PCI_INFO(pci_info, 1); 294 set_next_law(pci_info.mem_phys, 295 law_size_bits(pci_info.mem_size), pci_info.law); 296 set_next_law(pci_info.io_phys, 297 law_size_bits(pci_info.io_size), pci_info.law); 298 299 first_free_busno = fsl_pci_init_port(&pci_info, 300 &pci1_hose, first_free_busno); 301 } else { 302 printf("PCI: disabled\n"); 303 } 304 305 puts("\n"); 306 #else 307 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 308 #endif 309 310 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ 311 312 fsl_pcie_init_board(first_free_busno); 313 } 314 #endif 315 316 int board_eth_init(bd_t *bis) 317 { 318 tsec_standard_init(bis); 319 pci_eth_init(bis); 320 return 0; /* otherwise cpu_eth_init gets run */ 321 } 322 323 int last_stage_init(void) 324 { 325 return 0; 326 } 327 328 #if defined(CONFIG_OF_BOARD_SETUP) 329 void ft_board_setup(void *blob, bd_t *bd) 330 { 331 ft_cpu_setup(blob, bd); 332 333 #ifdef CONFIG_FSL_PCI_INIT 334 FT_FSL_PCI_SETUP; 335 #endif 336 } 337 #endif 338