1 /* 2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * 5 * Copyright 2004, 2007 Freescale Semiconductor. 6 * 7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <pci.h> 30 #include <asm/processor.h> 31 #include <asm/immap_85xx.h> 32 #include <asm/immap_fsl_pci.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 39 extern void ddr_enable_ecc(unsigned int dram_size); 40 #endif 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 extern long int spd_sdram(void); 45 46 void local_bus_init(void); 47 void sdram_init(void); 48 long int fixed_sdram (void); 49 50 int board_early_init_f (void) 51 { 52 return 0; 53 } 54 55 int checkboard (void) 56 { 57 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 58 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); 59 60 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 61 (volatile)(*(u_char *)CFG_BD_REV) >> 4); 62 63 /* 64 * Initialize local bus. 65 */ 66 local_bus_init (); 67 68 /* 69 * Fix CPU2 errata: A core hang possible while executing a 70 * msync instruction and a snoopable transaction from an I/O 71 * master tagged to make quick forward progress is present. 72 */ 73 ecm->eebpcr |= (1 << 16); 74 75 /* 76 * Hack TSEC 3 and 4 IO voltages. 77 */ 78 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 79 80 ecm->eedr = 0xffffffff; /* clear ecm errors */ 81 ecm->eeer = 0xffffffff; /* enable ecm errors */ 82 return 0; 83 } 84 85 long int 86 initdram(int board_type) 87 { 88 long dram_size = 0; 89 90 puts("Initializing\n"); 91 92 #if defined(CONFIG_DDR_DLL) 93 { 94 /* 95 * Work around to stabilize DDR DLL MSYNC_IN. 96 * Errata DDR9 seems to have been fixed. 97 * This is now the workaround for Errata DDR11: 98 * Override DLL = 1, Course Adj = 1, Tap Select = 0 99 */ 100 101 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 102 103 gur->ddrdllcr = 0x81000000; 104 asm("sync;isync;msync"); 105 udelay(200); 106 } 107 #endif 108 109 #if defined(CONFIG_SPD_EEPROM) 110 dram_size = spd_sdram (); 111 #else 112 dram_size = fixed_sdram (); 113 #endif 114 115 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 116 /* 117 * Initialize and enable DDR ECC. 118 */ 119 ddr_enable_ecc(dram_size); 120 #endif 121 /* 122 * SDRAM Initialization 123 */ 124 sdram_init(); 125 126 puts(" DDR: "); 127 return dram_size; 128 } 129 130 /* 131 * Initialize Local Bus 132 */ 133 void 134 local_bus_init(void) 135 { 136 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 137 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 138 139 uint clkdiv; 140 uint lbc_hz; 141 sys_info_t sysinfo; 142 143 get_sys_info(&sysinfo); 144 clkdiv = (lbc->lcrr & 0x0f) * 2; 145 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 146 147 gur->lbiuiplldcr1 = 0x00078080; 148 if (clkdiv == 16) { 149 gur->lbiuiplldcr0 = 0x7c0f1bf0; 150 } else if (clkdiv == 8) { 151 gur->lbiuiplldcr0 = 0x6c0f1bf0; 152 } else if (clkdiv == 4) { 153 gur->lbiuiplldcr0 = 0x5c0f1bf0; 154 } 155 156 lbc->lcrr |= 0x00030000; 157 158 asm("sync;isync;msync"); 159 160 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 161 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 162 } 163 164 /* 165 * Initialize SDRAM memory on the Local Bus. 166 */ 167 void 168 sdram_init(void) 169 { 170 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) 171 172 uint idx; 173 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 174 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 175 uint lsdmr_common; 176 177 puts(" SDRAM: "); 178 179 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 180 181 /* 182 * Setup SDRAM Base and Option Registers 183 */ 184 lbc->or3 = CFG_OR3_PRELIM; 185 asm("msync"); 186 187 lbc->br3 = CFG_BR3_PRELIM; 188 asm("msync"); 189 190 lbc->lbcr = CFG_LBC_LBCR; 191 asm("msync"); 192 193 194 lbc->lsrt = CFG_LBC_LSRT; 195 lbc->mrtpr = CFG_LBC_MRTPR; 196 asm("msync"); 197 198 /* 199 * MPC8548 uses "new" 15-16 style addressing. 200 */ 201 lsdmr_common = CFG_LBC_LSDMR_COMMON; 202 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 203 204 /* 205 * Issue PRECHARGE ALL command. 206 */ 207 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 208 asm("sync;msync"); 209 *sdram_addr = 0xff; 210 ppcDcbf((unsigned long) sdram_addr); 211 udelay(100); 212 213 /* 214 * Issue 8 AUTO REFRESH commands. 215 */ 216 for (idx = 0; idx < 8; idx++) { 217 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 218 asm("sync;msync"); 219 *sdram_addr = 0xff; 220 ppcDcbf((unsigned long) sdram_addr); 221 udelay(100); 222 } 223 224 /* 225 * Issue 8 MODE-set command. 226 */ 227 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 228 asm("sync;msync"); 229 *sdram_addr = 0xff; 230 ppcDcbf((unsigned long) sdram_addr); 231 udelay(100); 232 233 /* 234 * Issue NORMAL OP command. 235 */ 236 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 237 asm("sync;msync"); 238 *sdram_addr = 0xff; 239 ppcDcbf((unsigned long) sdram_addr); 240 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 241 242 #endif /* enable SDRAM init */ 243 } 244 245 #if defined(CFG_DRAM_TEST) 246 int 247 testdram(void) 248 { 249 uint *pstart = (uint *) CFG_MEMTEST_START; 250 uint *pend = (uint *) CFG_MEMTEST_END; 251 uint *p; 252 253 printf("Testing DRAM from 0x%08x to 0x%08x\n", 254 CFG_MEMTEST_START, 255 CFG_MEMTEST_END); 256 257 printf("DRAM test phase 1:\n"); 258 for (p = pstart; p < pend; p++) 259 *p = 0xaaaaaaaa; 260 261 for (p = pstart; p < pend; p++) { 262 if (*p != 0xaaaaaaaa) { 263 printf ("DRAM test fails at: %08x\n", (uint) p); 264 return 1; 265 } 266 } 267 268 printf("DRAM test phase 2:\n"); 269 for (p = pstart; p < pend; p++) 270 *p = 0x55555555; 271 272 for (p = pstart; p < pend; p++) { 273 if (*p != 0x55555555) { 274 printf ("DRAM test fails at: %08x\n", (uint) p); 275 return 1; 276 } 277 } 278 279 printf("DRAM test passed.\n"); 280 return 0; 281 } 282 #endif 283 284 #if !defined(CONFIG_SPD_EEPROM) 285 /************************************************************************* 286 * fixed_sdram init -- doesn't use serial presence detect. 287 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 288 ************************************************************************/ 289 long int fixed_sdram (void) 290 { 291 #define CFG_DDR_CONTROL 0xc300c000 292 293 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); 294 295 ddr->cs0_bnds = 0x0000007f; 296 ddr->cs1_bnds = 0x008000ff; 297 ddr->cs2_bnds = 0x00000000; 298 ddr->cs3_bnds = 0x00000000; 299 ddr->cs0_config = 0x80010101; 300 ddr->cs1_config = 0x80010101; 301 ddr->cs2_config = 0x00000000; 302 ddr->cs3_config = 0x00000000; 303 ddr->ext_refrec = 0x00000000; 304 ddr->timing_cfg_0 = 0x00220802; 305 ddr->timing_cfg_1 = 0x38377322; 306 ddr->timing_cfg_2 = 0x0fa044C7; 307 ddr->sdram_cfg = 0x4300C000; 308 ddr->sdram_cfg_2 = 0x24401000; 309 ddr->sdram_mode = 0x23C00542; 310 ddr->sdram_mode_2 = 0x00000000; 311 ddr->sdram_interval = 0x05080100; 312 ddr->sdram_md_cntl = 0x00000000; 313 ddr->sdram_data_init = 0x00000000; 314 ddr->sdram_clk_cntl = 0x03800000; 315 asm("sync;isync;msync"); 316 udelay(500); 317 318 #if defined (CONFIG_DDR_ECC) 319 /* Enable ECC checking */ 320 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); 321 #else 322 ddr->sdram_cfg = CFG_DDR_CONTROL; 323 #endif 324 325 return CFG_SDRAM_SIZE * 1024 * 1024; 326 } 327 #endif 328 329 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 330 /* For some reason the Tundra PCI bridge shows up on itself as a 331 * different device. Work around that by refusing to configure it. 332 */ 333 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 334 335 static struct pci_config_table pci_sbc8548_config_table[] = { 336 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 337 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 338 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 339 mpc85xx_config_via_usbide, {0,0,0}}, 340 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 341 mpc85xx_config_via_usb, {0,0,0}}, 342 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 343 mpc85xx_config_via_usb2, {0,0,0}}, 344 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 345 mpc85xx_config_via_power, {0,0,0}}, 346 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 347 mpc85xx_config_via_ac97, {0,0,0}}, 348 {}, 349 }; 350 351 static struct pci_controller pci1_hose = { 352 config_table: pci_sbc8548_config_table}; 353 #endif /* CONFIG_PCI */ 354 355 #ifdef CONFIG_PCI2 356 static struct pci_controller pci2_hose; 357 #endif /* CONFIG_PCI2 */ 358 359 #ifdef CONFIG_PCIE1 360 static struct pci_controller pcie1_hose; 361 #endif /* CONFIG_PCIE1 */ 362 363 int first_free_busno=0; 364 365 void 366 pci_init_board(void) 367 { 368 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 369 370 #ifdef CONFIG_PCI1 371 { 372 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 373 extern void fsl_pci_init(struct pci_controller *hose); 374 struct pci_controller *hose = &pci1_hose; 375 struct pci_config_table *table; 376 377 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 378 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 379 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 380 381 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 382 383 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 384 385 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 386 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 387 (pci_32) ? 32 : 64, 388 (pci_speed == 33333000) ? "33" : 389 (pci_speed == 66666000) ? "66" : "unknown", 390 pci_clk_sel ? "sync" : "async", 391 pci_agent ? "agent" : "host", 392 pci_arb ? "arbiter" : "external-arbiter" 393 ); 394 395 396 /* inbound */ 397 pci_set_region(hose->regions + 0, 398 CFG_PCI_MEMORY_BUS, 399 CFG_PCI_MEMORY_PHYS, 400 CFG_PCI_MEMORY_SIZE, 401 PCI_REGION_MEM | PCI_REGION_MEMORY); 402 403 404 /* outbound memory */ 405 pci_set_region(hose->regions + 1, 406 CFG_PCI1_MEM_BASE, 407 CFG_PCI1_MEM_PHYS, 408 CFG_PCI1_MEM_SIZE, 409 PCI_REGION_MEM); 410 411 /* outbound io */ 412 pci_set_region(hose->regions + 2, 413 CFG_PCI1_IO_BASE, 414 CFG_PCI1_IO_PHYS, 415 CFG_PCI1_IO_SIZE, 416 PCI_REGION_IO); 417 hose->region_count = 3; 418 419 /* relocate config table pointers */ 420 hose->config_table = \ 421 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); 422 for (table = hose->config_table; table && table->vendor; table++) 423 table->config_device += gd->reloc_off; 424 425 hose->first_busno=first_free_busno; 426 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 427 428 fsl_pci_init(hose); 429 first_free_busno=hose->last_busno+1; 430 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 431 #ifdef CONFIG_PCIX_CHECK 432 if (!(gur->pordevsr & PORDEVSR_PCI)) { 433 /* PCI-X init */ 434 if (CONFIG_SYS_CLK_FREQ < 66000000) 435 printf("PCI-X will only work at 66 MHz\n"); 436 437 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 438 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 439 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 440 } 441 #endif 442 } else { 443 printf (" PCI: disabled\n"); 444 } 445 } 446 #else 447 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 448 #endif 449 450 #ifdef CONFIG_PCI2 451 { 452 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ 453 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 454 if (pci_dual) { 455 printf (" PCI2: 32 bit, 66 MHz, %s\n", 456 pci2_clk_sel ? "sync" : "async"); 457 } else { 458 printf (" PCI2: disabled\n"); 459 } 460 } 461 #else 462 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ 463 #endif /* CONFIG_PCI2 */ 464 465 #ifdef CONFIG_PCIE1 466 { 467 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 468 extern void fsl_pci_init(struct pci_controller *hose); 469 struct pci_controller *hose = &pcie1_hose; 470 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 471 472 int pcie_configured = io_sel >= 1; 473 474 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 475 printf ("\n PCIE connected to slot as %s (base address %x)", 476 pcie_ep ? "End Point" : "Root Complex", 477 (uint)pci); 478 479 if (pci->pme_msg_det) { 480 pci->pme_msg_det = 0xffffffff; 481 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 482 } 483 printf ("\n"); 484 485 /* inbound */ 486 pci_set_region(hose->regions + 0, 487 CFG_PCI_MEMORY_BUS, 488 CFG_PCI_MEMORY_PHYS, 489 CFG_PCI_MEMORY_SIZE, 490 PCI_REGION_MEM | PCI_REGION_MEMORY); 491 492 /* outbound memory */ 493 pci_set_region(hose->regions + 1, 494 CFG_PCIE1_MEM_BASE, 495 CFG_PCIE1_MEM_PHYS, 496 CFG_PCIE1_MEM_SIZE, 497 PCI_REGION_MEM); 498 499 /* outbound io */ 500 pci_set_region(hose->regions + 2, 501 CFG_PCIE1_IO_BASE, 502 CFG_PCIE1_IO_PHYS, 503 CFG_PCIE1_IO_SIZE, 504 PCI_REGION_IO); 505 506 hose->region_count = 3; 507 508 hose->first_busno=first_free_busno; 509 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 510 511 fsl_pci_init(hose); 512 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); 513 514 first_free_busno=hose->last_busno+1; 515 516 } else { 517 printf (" PCIE: disabled\n"); 518 } 519 } 520 #else 521 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 522 #endif 523 524 } 525 526 int last_stage_init(void) 527 { 528 return 0; 529 } 530 531 #if defined(CONFIG_OF_BOARD_SETUP) 532 void 533 ft_pci_setup(void *blob, bd_t *bd) 534 { 535 int node, tmp[2]; 536 const char *path; 537 538 node = fdt_path_offset(blob, "/aliases"); 539 tmp[0] = 0; 540 if (node >= 0) { 541 #ifdef CONFIG_PCI1 542 path = fdt_getprop(blob, node, "pci0", NULL); 543 if (path) { 544 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 545 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 546 } 547 #endif 548 #ifdef CONFIG_PCIE1 549 path = fdt_getprop(blob, node, "pci1", NULL); 550 if (path) { 551 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 552 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 553 } 554 #endif 555 } 556 } 557 #endif 558 559 #if defined(CONFIG_OF_BOARD_SETUP) 560 void 561 ft_board_setup(void *blob, bd_t *bd) 562 { 563 ft_cpu_setup(blob, bd); 564 #ifdef CONFIG_PCI 565 ft_pci_setup(blob, bd); 566 #endif 567 } 568 #endif 569