1 /* 2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> 3 * 4 * Copyright 2007 Embedded Specialties, Inc. 5 * 6 * Copyright 2004, 2007 Freescale Semiconductor. 7 * 8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <pci.h> 31 #include <asm/processor.h> 32 #include <asm/immap_85xx.h> 33 #include <asm/fsl_pci.h> 34 #include <asm/fsl_ddr_sdram.h> 35 #include <spd_sdram.h> 36 #include <netdev.h> 37 #include <tsec.h> 38 #include <miiphy.h> 39 #include <libfdt.h> 40 #include <fdt_support.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 void local_bus_init(void); 45 void sdram_init(void); 46 long int fixed_sdram (void); 47 48 int board_early_init_f (void) 49 { 50 return 0; 51 } 52 53 int checkboard (void) 54 { 55 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 56 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; 57 58 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", 59 in_8(rev) >> 4); 60 61 /* 62 * Initialize local bus. 63 */ 64 local_bus_init (); 65 66 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ 67 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ 68 return 0; 69 } 70 71 phys_size_t 72 initdram(int board_type) 73 { 74 long dram_size = 0; 75 76 puts("Initializing\n"); 77 78 #if defined(CONFIG_DDR_DLL) 79 { 80 /* 81 * Work around to stabilize DDR DLL MSYNC_IN. 82 * Errata DDR9 seems to have been fixed. 83 * This is now the workaround for Errata DDR11: 84 * Override DLL = 1, Course Adj = 1, Tap Select = 0 85 */ 86 87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 88 89 out_be32(&gur->ddrdllcr, 0x81000000); 90 asm("sync;isync;msync"); 91 udelay(200); 92 } 93 #endif 94 95 #if defined(CONFIG_SPD_EEPROM) 96 dram_size = fsl_ddr_sdram(); 97 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 98 dram_size *= 0x100000; 99 #else 100 dram_size = fixed_sdram (); 101 #endif 102 103 /* 104 * SDRAM Initialization 105 */ 106 sdram_init(); 107 108 puts(" DDR: "); 109 return dram_size; 110 } 111 112 /* 113 * Initialize Local Bus 114 */ 115 void 116 local_bus_init(void) 117 { 118 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 119 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 120 121 uint clkdiv; 122 uint lbc_hz; 123 sys_info_t sysinfo; 124 125 get_sys_info(&sysinfo); 126 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; 127 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 128 129 out_be32(&gur->lbiuiplldcr1, 0x00078080); 130 if (clkdiv == 16) { 131 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 132 } else if (clkdiv == 8) { 133 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 134 } else if (clkdiv == 4) { 135 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 136 } 137 138 setbits_be32(&lbc->lcrr, 0x00030000); 139 140 asm("sync;isync;msync"); 141 142 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ 143 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ 144 } 145 146 /* 147 * Initialize SDRAM memory on the Local Bus. 148 */ 149 void 150 sdram_init(void) 151 { 152 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) 153 154 uint idx; 155 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 156 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 157 uint lsdmr_common; 158 159 puts(" SDRAM: "); 160 161 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 162 163 /* 164 * Setup SDRAM Base and Option Registers 165 */ 166 out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); 167 asm("msync"); 168 169 out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); 170 asm("msync"); 171 172 out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM); 173 asm("msync"); 174 175 out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM); 176 asm("msync"); 177 178 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); 179 asm("msync"); 180 181 182 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); 183 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); 184 asm("msync"); 185 186 /* 187 * MPC8548 uses "new" 15-16 style addressing. 188 */ 189 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 190 lsdmr_common |= LSDMR_BSMA1516; 191 192 /* 193 * Issue PRECHARGE ALL command. 194 */ 195 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); 196 asm("sync;msync"); 197 *sdram_addr = 0xff; 198 ppcDcbf((unsigned long) sdram_addr); 199 udelay(100); 200 201 /* 202 * Issue 8 AUTO REFRESH commands. 203 */ 204 for (idx = 0; idx < 8; idx++) { 205 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); 206 asm("sync;msync"); 207 *sdram_addr = 0xff; 208 ppcDcbf((unsigned long) sdram_addr); 209 udelay(100); 210 } 211 212 /* 213 * Issue 8 MODE-set command. 214 */ 215 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); 216 asm("sync;msync"); 217 *sdram_addr = 0xff; 218 ppcDcbf((unsigned long) sdram_addr); 219 udelay(100); 220 221 /* 222 * Issue NORMAL OP command. 223 */ 224 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); 225 asm("sync;msync"); 226 *sdram_addr = 0xff; 227 ppcDcbf((unsigned long) sdram_addr); 228 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 229 230 #endif /* enable SDRAM init */ 231 } 232 233 #if defined(CONFIG_SYS_DRAM_TEST) 234 int 235 testdram(void) 236 { 237 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 238 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 239 uint *p; 240 241 printf("Testing DRAM from 0x%08x to 0x%08x\n", 242 CONFIG_SYS_MEMTEST_START, 243 CONFIG_SYS_MEMTEST_END); 244 245 printf("DRAM test phase 1:\n"); 246 for (p = pstart; p < pend; p++) 247 *p = 0xaaaaaaaa; 248 249 for (p = pstart; p < pend; p++) { 250 if (*p != 0xaaaaaaaa) { 251 printf ("DRAM test fails at: %08x\n", (uint) p); 252 return 1; 253 } 254 } 255 256 printf("DRAM test phase 2:\n"); 257 for (p = pstart; p < pend; p++) 258 *p = 0x55555555; 259 260 for (p = pstart; p < pend; p++) { 261 if (*p != 0x55555555) { 262 printf ("DRAM test fails at: %08x\n", (uint) p); 263 return 1; 264 } 265 } 266 267 printf("DRAM test passed.\n"); 268 return 0; 269 } 270 #endif 271 272 #if !defined(CONFIG_SPD_EEPROM) 273 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 274 /************************************************************************* 275 * fixed_sdram init -- doesn't use serial presence detect. 276 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 277 ************************************************************************/ 278 long int fixed_sdram (void) 279 { 280 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); 281 282 out_be32(&ddr->cs0_bnds, 0x0000007f); 283 out_be32(&ddr->cs1_bnds, 0x008000ff); 284 out_be32(&ddr->cs2_bnds, 0x00000000); 285 out_be32(&ddr->cs3_bnds, 0x00000000); 286 out_be32(&ddr->cs0_config, 0x80010101); 287 out_be32(&ddr->cs1_config, 0x80010101); 288 out_be32(&ddr->cs2_config, 0x00000000); 289 out_be32(&ddr->cs3_config, 0x00000000); 290 out_be32(&ddr->timing_cfg_3, 0x00000000); 291 out_be32(&ddr->timing_cfg_0, 0x00220802); 292 out_be32(&ddr->timing_cfg_1, 0x38377322); 293 out_be32(&ddr->timing_cfg_2, 0x0fa044C7); 294 out_be32(&ddr->sdram_cfg, 0x4300C000); 295 out_be32(&ddr->sdram_cfg_2, 0x24401000); 296 out_be32(&ddr->sdram_mode, 0x23C00542); 297 out_be32(&ddr->sdram_mode_2, 0x00000000); 298 out_be32(&ddr->sdram_interval, 0x05080100); 299 out_be32(&ddr->sdram_md_cntl, 0x00000000); 300 out_be32(&ddr->sdram_data_init, 0x00000000); 301 out_be32(&ddr->sdram_clk_cntl, 0x03800000); 302 asm("sync;isync;msync"); 303 udelay(500); 304 305 #if defined (CONFIG_DDR_ECC) 306 /* Enable ECC checking */ 307 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); 308 #else 309 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 310 #endif 311 312 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 313 } 314 #endif 315 316 #ifdef CONFIG_PCI1 317 static struct pci_controller pci1_hose; 318 #endif /* CONFIG_PCI1 */ 319 320 #ifdef CONFIG_PCIE1 321 static struct pci_controller pcie1_hose; 322 #endif /* CONFIG_PCIE1 */ 323 324 325 #ifdef CONFIG_PCI 326 void 327 pci_init_board(void) 328 { 329 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 330 struct fsl_pci_info pci_info[2]; 331 u32 devdisr, pordevsr, porpllsr, io_sel; 332 int first_free_busno = 0; 333 int num = 0; 334 335 #ifdef CONFIG_PCIE1 336 int pcie_configured; 337 #endif 338 339 devdisr = in_be32(&gur->devdisr); 340 pordevsr = in_be32(&gur->pordevsr); 341 porpllsr = in_be32(&gur->porpllsr); 342 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 343 344 debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 345 346 #ifdef CONFIG_PCI1 347 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 348 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; 349 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 350 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 351 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ 352 353 printf (" PCI host: %d bit, %s MHz, %s, %s\n", 354 (pci_32) ? 32 : 64, 355 (pci_speed == 33000000) ? "33" : 356 (pci_speed == 66000000) ? "66" : "unknown", 357 pci_clk_sel ? "sync" : "async", 358 pci_arb ? "arbiter" : "external-arbiter"); 359 360 SET_STD_PCI_INFO(pci_info[num], 1); 361 first_free_busno = fsl_pci_init_port(&pci_info[num++], 362 &pci1_hose, first_free_busno); 363 } else { 364 printf (" PCI: disabled\n"); 365 } 366 367 puts("\n"); 368 #else 369 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 370 #endif 371 372 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ 373 374 #ifdef CONFIG_PCIE1 375 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 376 377 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 378 SET_STD_PCIE_INFO(pci_info[num], 1); 379 printf (" PCIE at base address %lx\n", pci_info[num].regs); 380 first_free_busno = fsl_pci_init_port(&pci_info[num++], 381 &pcie1_hose, first_free_busno); 382 } else { 383 printf (" PCIE: disabled\n"); 384 } 385 386 puts("\n"); 387 #else 388 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 389 #endif 390 } 391 #endif 392 393 int board_eth_init(bd_t *bis) 394 { 395 tsec_standard_init(bis); 396 pci_eth_init(bis); 397 return 0; /* otherwise cpu_eth_init gets run */ 398 } 399 400 int last_stage_init(void) 401 { 402 return 0; 403 } 404 405 #if defined(CONFIG_OF_BOARD_SETUP) 406 void ft_board_setup(void *blob, bd_t *bd) 407 { 408 ft_cpu_setup(blob, bd); 409 #ifdef CONFIG_PCI1 410 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 411 #endif 412 #ifdef CONFIG_PCIE1 413 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 414 #endif 415 } 416 #endif 417