1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2008 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 9 #include <fsl_ddr_sdram.h> 10 #include <fsl_ddr_dimm_params.h> 11 12 void fsl_ddr_board_options(memctl_options_t *popts, 13 dimm_params_t *pdimm, 14 unsigned int ctrl_num) 15 { 16 /* 17 * Factors to consider for clock adjust: 18 * - number of chips on bus 19 * - position of slot 20 * - DDR1 vs. DDR2? 21 * - ??? 22 * 23 * This needs to be determined on a board-by-board basis. 24 * 0110 3/4 cycle late 25 * 0111 7/8 cycle late 26 */ 27 popts->clk_adjust = 7; 28 29 /* 30 * Factors to consider for CPO: 31 * - frequency 32 * - ddr1 vs. ddr2 33 */ 34 popts->cpo_override = 10; 35 36 /* 37 * Factors to consider for write data delay: 38 * - number of DIMMs 39 * 40 * 1 = 1/4 clock delay 41 * 2 = 1/2 clock delay 42 * 3 = 3/4 clock delay 43 * 4 = 1 clock delay 44 * 5 = 5/4 clock delay 45 * 6 = 3/2 clock delay 46 */ 47 popts->write_data_delay = 3; 48 49 /* 50 * Factors to consider for half-strength driver enable: 51 * - number of DIMMs installed 52 */ 53 popts->half_strength_driver_enable = 0; 54 } 55 56 #ifdef CONFIG_SPD_EEPROM 57 /* 58 * Workaround for hardware errata. An i2c address conflict 59 * existed on earlier boards; the workaround moved the DDR 60 * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and 61 * if that fails, then fall back to reading at 0x51. 62 */ 63 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) 64 { 65 int ret; 66 67 #ifdef ALT_SPD_EEPROM_ADDRESS 68 if (i2c_address == SPD_EEPROM_ADDRESS) { 69 ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd, 70 sizeof(generic_spd_eeprom_t)); 71 if (ret == 0) 72 return; /* Good data at 0x53 */ 73 memset(spd, 0, sizeof(generic_spd_eeprom_t)); 74 } 75 #endif 76 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 77 sizeof(generic_spd_eeprom_t)); 78 if (ret) { 79 printf("DDR: failed to read SPD from addr %u\n", i2c_address); 80 memset(spd, 0, sizeof(generic_spd_eeprom_t)); 81 } 82 } 83 84 #else 85 /* 86 * fixed_sdram init -- doesn't use serial presence detect. 87 * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 88 */ 89 phys_size_t fixed_sdram(void) 90 { 91 struct ccsr_ddr __iomem *ddr = 92 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 93 94 out_be32(&ddr->cs0_bnds, 0x0000007f); 95 out_be32(&ddr->cs1_bnds, 0x008000ff); 96 out_be32(&ddr->cs2_bnds, 0x00000000); 97 out_be32(&ddr->cs3_bnds, 0x00000000); 98 99 out_be32(&ddr->cs0_config, 0x80010101); 100 out_be32(&ddr->cs1_config, 0x80010101); 101 out_be32(&ddr->cs2_config, 0x00000000); 102 out_be32(&ddr->cs3_config, 0x00000000); 103 104 out_be32(&ddr->timing_cfg_3, 0x00000000); 105 out_be32(&ddr->timing_cfg_0, 0x00220802); 106 out_be32(&ddr->timing_cfg_1, 0x38377322); 107 out_be32(&ddr->timing_cfg_2, 0x0fa044C7); 108 109 out_be32(&ddr->sdram_cfg, 0x4300C000); 110 out_be32(&ddr->sdram_cfg_2, 0x24401000); 111 112 out_be32(&ddr->sdram_mode, 0x23C00542); 113 out_be32(&ddr->sdram_mode_2, 0x00000000); 114 115 out_be32(&ddr->sdram_interval, 0x05080100); 116 out_be32(&ddr->sdram_md_cntl, 0x00000000); 117 out_be32(&ddr->sdram_data_init, 0x00000000); 118 out_be32(&ddr->sdram_clk_cntl, 0x03800000); 119 asm("sync;isync;msync"); 120 udelay(500); 121 122 #ifdef CONFIG_DDR_ECC 123 /* Enable ECC checking */ 124 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); 125 #else 126 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 127 #endif 128 129 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 130 } 131 #endif 132