1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 12 #include <fsl_ddr_sdram.h> 13 #include <fsl_ddr_dimm_params.h> 14 15 void fsl_ddr_board_options(memctl_options_t *popts, 16 dimm_params_t *pdimm, 17 unsigned int ctrl_num) 18 { 19 /* 20 * Factors to consider for clock adjust: 21 * - number of chips on bus 22 * - position of slot 23 * - DDR1 vs. DDR2? 24 * - ??? 25 * 26 * This needs to be determined on a board-by-board basis. 27 * 0110 3/4 cycle late 28 * 0111 7/8 cycle late 29 */ 30 popts->clk_adjust = 7; 31 32 /* 33 * Factors to consider for CPO: 34 * - frequency 35 * - ddr1 vs. ddr2 36 */ 37 popts->cpo_override = 10; 38 39 /* 40 * Factors to consider for write data delay: 41 * - number of DIMMs 42 * 43 * 1 = 1/4 clock delay 44 * 2 = 1/2 clock delay 45 * 3 = 3/4 clock delay 46 * 4 = 1 clock delay 47 * 5 = 5/4 clock delay 48 * 6 = 3/2 clock delay 49 */ 50 popts->write_data_delay = 3; 51 52 /* 53 * Factors to consider for half-strength driver enable: 54 * - number of DIMMs installed 55 */ 56 popts->half_strength_driver_enable = 0; 57 } 58 59 #ifdef CONFIG_SPD_EEPROM 60 /* 61 * Workaround for hardware errata. An i2c address conflict 62 * existed on earlier boards; the workaround moved the DDR 63 * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and 64 * if that fails, then fall back to reading at 0x51. 65 */ 66 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) 67 { 68 int ret; 69 70 #ifdef ALT_SPD_EEPROM_ADDRESS 71 if (i2c_address == SPD_EEPROM_ADDRESS) { 72 ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd, 73 sizeof(generic_spd_eeprom_t)); 74 if (ret == 0) 75 return; /* Good data at 0x53 */ 76 memset(spd, 0, sizeof(generic_spd_eeprom_t)); 77 } 78 #endif 79 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 80 sizeof(generic_spd_eeprom_t)); 81 if (ret) { 82 printf("DDR: failed to read SPD from addr %u\n", i2c_address); 83 memset(spd, 0, sizeof(generic_spd_eeprom_t)); 84 } 85 } 86 87 #else 88 /* 89 * fixed_sdram init -- doesn't use serial presence detect. 90 * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. 91 */ 92 phys_size_t fixed_sdram(void) 93 { 94 struct ccsr_ddr __iomem *ddr = 95 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 96 97 out_be32(&ddr->cs0_bnds, 0x0000007f); 98 out_be32(&ddr->cs1_bnds, 0x008000ff); 99 out_be32(&ddr->cs2_bnds, 0x00000000); 100 out_be32(&ddr->cs3_bnds, 0x00000000); 101 102 out_be32(&ddr->cs0_config, 0x80010101); 103 out_be32(&ddr->cs1_config, 0x80010101); 104 out_be32(&ddr->cs2_config, 0x00000000); 105 out_be32(&ddr->cs3_config, 0x00000000); 106 107 out_be32(&ddr->timing_cfg_3, 0x00000000); 108 out_be32(&ddr->timing_cfg_0, 0x00220802); 109 out_be32(&ddr->timing_cfg_1, 0x38377322); 110 out_be32(&ddr->timing_cfg_2, 0x0fa044C7); 111 112 out_be32(&ddr->sdram_cfg, 0x4300C000); 113 out_be32(&ddr->sdram_cfg_2, 0x24401000); 114 115 out_be32(&ddr->sdram_mode, 0x23C00542); 116 out_be32(&ddr->sdram_mode_2, 0x00000000); 117 118 out_be32(&ddr->sdram_interval, 0x05080100); 119 out_be32(&ddr->sdram_md_cntl, 0x00000000); 120 out_be32(&ddr->sdram_data_init, 0x00000000); 121 out_be32(&ddr->sdram_clk_cntl, 0x03800000); 122 asm("sync;isync;msync"); 123 udelay(500); 124 125 #ifdef CONFIG_DDR_ECC 126 /* Enable ECC checking */ 127 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); 128 #else 129 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 130 #endif 131 132 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 133 } 134 #endif 135