1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 12 #include <asm/fsl_ddr_sdram.h> 13 #include <asm/fsl_ddr_dimm_params.h> 14 15 static void 16 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) 17 { 18 i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); 19 } 20 21 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, 22 unsigned int ctrl_num) 23 { 24 unsigned int i; 25 26 if (ctrl_num) { 27 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 28 return; 29 } 30 31 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 32 get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); 33 } 34 } 35 36 void fsl_ddr_board_options(memctl_options_t *popts, 37 dimm_params_t *pdimm, 38 unsigned int ctrl_num) 39 { 40 /* 41 * Factors to consider for clock adjust: 42 * - number of chips on bus 43 * - position of slot 44 * - DDR1 vs. DDR2? 45 * - ??? 46 * 47 * This needs to be determined on a board-by-board basis. 48 * 0110 3/4 cycle late 49 * 0111 7/8 cycle late 50 */ 51 popts->clk_adjust = 7; 52 53 /* 54 * Factors to consider for CPO: 55 * - frequency 56 * - ddr1 vs. ddr2 57 */ 58 popts->cpo_override = 10; 59 60 /* 61 * Factors to consider for write data delay: 62 * - number of DIMMs 63 * 64 * 1 = 1/4 clock delay 65 * 2 = 1/2 clock delay 66 * 3 = 3/4 clock delay 67 * 4 = 1 clock delay 68 * 5 = 5/4 clock delay 69 * 6 = 3/2 clock delay 70 */ 71 popts->write_data_delay = 3; 72 73 /* 74 * Factors to consider for half-strength driver enable: 75 * - number of DIMMs installed 76 */ 77 popts->half_strength_driver_enable = 0; 78 } 79