1 /* 2 * sbc8349.c -- WindRiver SBC8349 board support. 3 * Copyright (c) 2006-2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 * 26 */ 27 28 #include <common.h> 29 #include <ioports.h> 30 #include <mpc83xx.h> 31 #include <asm/mpc8349_pci.h> 32 #include <i2c.h> 33 #include <spd_sdram.h> 34 #include <miiphy.h> 35 #if defined(CONFIG_OF_LIBFDT) 36 #include <libfdt.h> 37 #endif 38 39 int fixed_sdram(void); 40 void sdram_init(void); 41 42 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) 43 void ddr_enable_ecc(unsigned int dram_size); 44 #endif 45 46 #ifdef CONFIG_BOARD_EARLY_INIT_F 47 int board_early_init_f (void) 48 { 49 return 0; 50 } 51 #endif 52 53 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 54 55 phys_size_t initdram (int board_type) 56 { 57 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 58 u32 msize = 0; 59 60 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 61 return -1; 62 63 /* DDR SDRAM - Main SODIMM */ 64 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 65 #if defined(CONFIG_SPD_EEPROM) 66 msize = spd_sdram(); 67 #else 68 msize = fixed_sdram(); 69 #endif 70 /* 71 * Initialize SDRAM if it is on local bus. 72 */ 73 sdram_init(); 74 75 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 76 /* 77 * Initialize and enable DDR ECC. 78 */ 79 ddr_enable_ecc(msize * 1024 * 1024); 80 #endif 81 /* return total bus SDRAM size(bytes) -- DDR */ 82 return (msize * 1024 * 1024); 83 } 84 85 #if !defined(CONFIG_SPD_EEPROM) 86 /************************************************************************* 87 * fixed sdram init -- doesn't use serial presence detect. 88 ************************************************************************/ 89 int fixed_sdram(void) 90 { 91 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 92 u32 msize = CONFIG_SYS_DDR_SIZE; 93 u32 ddr_size = msize << 20; /* DDR size in bytes */ 94 u32 ddr_size_log2 = __ilog2(msize); 95 96 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 97 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 98 99 #if (CONFIG_SYS_DDR_SIZE != 256) 100 #warning Currently any ddr size other than 256 is not supported 101 #endif 102 103 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) 104 #warning Chip select bounds is only configurable in 16MB increments 105 #endif 106 im->ddr.csbnds[2].csbnds = 107 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | 108 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> 109 CSBNDS_EA_SHIFT) & CSBNDS_EA); 110 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; 111 112 /* currently we use only one CS, so disable the other banks */ 113 im->ddr.cs_config[0] = 0; 114 im->ddr.cs_config[1] = 0; 115 im->ddr.cs_config[3] = 0; 116 117 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 118 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 119 120 im->ddr.sdram_cfg = 121 SDRAM_CFG_SREN 122 #if defined(CONFIG_DDR_2T_TIMING) 123 | SDRAM_CFG_2T_EN 124 #endif 125 | SDRAM_CFG_SDRAM_TYPE_DDR1; 126 #if defined (CONFIG_DDR_32BIT) 127 /* for 32-bit mode burst length is 8 */ 128 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 129 #endif 130 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 131 132 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 133 udelay(200); 134 135 /* enable DDR controller */ 136 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 137 return msize; 138 } 139 #endif/*!CONFIG_SYS_SPD_EEPROM*/ 140 141 142 int checkboard (void) 143 { 144 puts("Board: Wind River SBC834x\n"); 145 return 0; 146 } 147 148 /* 149 * if board is fitted with SDRAM 150 */ 151 #if defined(CONFIG_SYS_BR2_PRELIM) \ 152 && defined(CONFIG_SYS_OR2_PRELIM) \ 153 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ 154 && defined(CONFIG_SYS_LBLAWAR2_PRELIM) 155 /* 156 * Initialize SDRAM memory on the Local Bus. 157 */ 158 159 void sdram_init(void) 160 { 161 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 162 volatile fsl_lbc_t *lbc = &immap->im_lbc; 163 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 164 165 puts("\n SDRAM on Local Bus: "); 166 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 167 168 /* 169 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 170 */ 171 172 /* setup mtrpt, lsrt and lbcr for LB bus */ 173 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 174 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 175 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 176 asm("sync"); 177 178 /* 179 * Configure the SDRAM controller Machine Mode Register. 180 */ 181 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 182 183 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 184 asm("sync"); 185 *sdram_addr = 0xff; 186 udelay(100); 187 188 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 189 asm("sync"); 190 /*1 times*/ 191 *sdram_addr = 0xff; 192 udelay(100); 193 /*2 times*/ 194 *sdram_addr = 0xff; 195 udelay(100); 196 /*3 times*/ 197 *sdram_addr = 0xff; 198 udelay(100); 199 /*4 times*/ 200 *sdram_addr = 0xff; 201 udelay(100); 202 /*5 times*/ 203 *sdram_addr = 0xff; 204 udelay(100); 205 /*6 times*/ 206 *sdram_addr = 0xff; 207 udelay(100); 208 /*7 times*/ 209 *sdram_addr = 0xff; 210 udelay(100); 211 /*8 times*/ 212 *sdram_addr = 0xff; 213 udelay(100); 214 215 /* 0x58636733; mode register write operation */ 216 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; 217 asm("sync"); 218 *sdram_addr = 0xff; 219 udelay(100); 220 221 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ 222 asm("sync"); 223 *sdram_addr = 0xff; 224 udelay(100); 225 } 226 #else 227 void sdram_init(void) 228 { 229 puts(" SDRAM on Local Bus: Disabled in config\n"); 230 } 231 #endif 232 233 #if defined(CONFIG_OF_BOARD_SETUP) 234 void ft_board_setup(void *blob, bd_t *bd) 235 { 236 ft_cpu_setup(blob, bd); 237 #ifdef CONFIG_PCI 238 ft_pci_setup(blob, bd); 239 #endif 240 } 241 #endif 242