xref: /openbmc/u-boot/board/sbc8349/sbc8349.c (revision 87a62bce)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * sbc8349.c -- WindRiver SBC8349 board support.
4  * Copyright (c) 2006-2007 Wind River Systems, Inc.
5  *
6  * Paul Gortmaker <paul.gortmaker@windriver.com>
7  * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
8  */
9 
10 #include <common.h>
11 #include <ioports.h>
12 #include <mpc83xx.h>
13 #include <asm/mpc8349_pci.h>
14 #include <i2c.h>
15 #include <spd_sdram.h>
16 #include <miiphy.h>
17 #if defined(CONFIG_OF_LIBFDT)
18 #include <linux/libfdt.h>
19 #endif
20 
21 DECLARE_GLOBAL_DATA_PTR;
22 
23 int fixed_sdram(void);
24 void sdram_init(void);
25 
26 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
27 void ddr_enable_ecc(unsigned int dram_size);
28 #endif
29 
30 #ifdef CONFIG_BOARD_EARLY_INIT_F
31 int board_early_init_f (void)
32 {
33 	return 0;
34 }
35 #endif
36 
37 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
38 
39 int dram_init(void)
40 {
41 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
42 	u32 msize = 0;
43 
44 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
45 		return -1;
46 
47 	/* DDR SDRAM - Main SODIMM */
48 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
49 #if defined(CONFIG_SPD_EEPROM)
50 	msize = spd_sdram();
51 #else
52 	msize = fixed_sdram();
53 #endif
54 	/*
55 	 * Initialize SDRAM if it is on local bus.
56 	 */
57 	sdram_init();
58 
59 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
60 	/*
61 	 * Initialize and enable DDR ECC.
62 	 */
63 	ddr_enable_ecc(msize * 1024 * 1024);
64 #endif
65 	/* set total bus SDRAM size(bytes)  -- DDR */
66 	gd->ram_size = msize * 1024 * 1024;
67 
68 	return 0;
69 }
70 
71 #if !defined(CONFIG_SPD_EEPROM)
72 /*************************************************************************
73  *  fixed sdram init -- doesn't use serial presence detect.
74  ************************************************************************/
75 int fixed_sdram(void)
76 {
77 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
78 	u32 msize = CONFIG_SYS_DDR_SIZE;
79 	u32 ddr_size = msize << 20;	/* DDR size in bytes */
80 	u32 ddr_size_log2 = __ilog2(msize);
81 
82 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
83 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
84 
85 #if (CONFIG_SYS_DDR_SIZE != 256)
86 #warning Currently any ddr size other than 256 is not supported
87 #endif
88 
89 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
90 #warning Chip select bounds is only configurable in 16MB increments
91 #endif
92 	im->ddr.csbnds[2].csbnds =
93 		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
94 		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
95 				CSBNDS_EA_SHIFT) & CSBNDS_EA);
96 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
97 
98 	/* currently we use only one CS, so disable the other banks */
99 	im->ddr.cs_config[0] = 0;
100 	im->ddr.cs_config[1] = 0;
101 	im->ddr.cs_config[3] = 0;
102 
103 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
104 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
105 
106 	im->ddr.sdram_cfg =
107 		SDRAM_CFG_SREN
108 #if defined(CONFIG_DDR_2T_TIMING)
109 		| SDRAM_CFG_2T_EN
110 #endif
111 		| SDRAM_CFG_SDRAM_TYPE_DDR1;
112 #if defined (CONFIG_DDR_32BIT)
113 	/* for 32-bit mode burst length is 8 */
114 	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
115 #endif
116 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
117 
118 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
119 	udelay(200);
120 
121 	/* enable DDR controller */
122 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
123 	return msize;
124 }
125 #endif/*!CONFIG_SYS_SPD_EEPROM*/
126 
127 
128 int checkboard (void)
129 {
130 	puts("Board: Wind River SBC834x\n");
131 	return 0;
132 }
133 
134 /*
135  * if board is fitted with SDRAM
136  */
137 #if defined(CONFIG_SYS_BR2_PRELIM)  \
138 	&& defined(CONFIG_SYS_OR2_PRELIM) \
139 	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
140 	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
141 /*
142  * Initialize SDRAM memory on the Local Bus.
143  */
144 
145 void sdram_init(void)
146 {
147 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
148 	volatile fsl_lbc_t *lbc = &immap->im_lbc;
149 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
150 
151 	puts("\n   SDRAM on Local Bus: ");
152 	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
153 
154 	/*
155 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
156 	 */
157 
158 	/* setup mtrpt, lsrt and lbcr for LB bus */
159 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
160 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
161 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
162 	asm("sync");
163 
164 	/*
165 	 * Configure the SDRAM controller Machine Mode Register.
166 	 */
167 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
168 
169 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
170 	asm("sync");
171 	*sdram_addr = 0xff;
172 	udelay(100);
173 
174 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
175 	asm("sync");
176 	/*1 times*/
177 	*sdram_addr = 0xff;
178 	udelay(100);
179 	/*2 times*/
180 	*sdram_addr = 0xff;
181 	udelay(100);
182 	/*3 times*/
183 	*sdram_addr = 0xff;
184 	udelay(100);
185 	/*4 times*/
186 	*sdram_addr = 0xff;
187 	udelay(100);
188 	/*5 times*/
189 	*sdram_addr = 0xff;
190 	udelay(100);
191 	/*6 times*/
192 	*sdram_addr = 0xff;
193 	udelay(100);
194 	/*7 times*/
195 	*sdram_addr = 0xff;
196 	udelay(100);
197 	/*8 times*/
198 	*sdram_addr = 0xff;
199 	udelay(100);
200 
201 	/* 0x58636733; mode register write operation */
202 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
203 	asm("sync");
204 	*sdram_addr = 0xff;
205 	udelay(100);
206 
207 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
208 	asm("sync");
209 	*sdram_addr = 0xff;
210 	udelay(100);
211 }
212 #else
213 void sdram_init(void)
214 {
215 	puts("   SDRAM on Local Bus: Disabled in config\n");
216 }
217 #endif
218 
219 #if defined(CONFIG_OF_BOARD_SETUP)
220 int ft_board_setup(void *blob, bd_t *bd)
221 {
222 	ft_cpu_setup(blob, bd);
223 #ifdef CONFIG_PCI
224 	ft_pci_setup(blob, bd);
225 #endif
226 
227 	return 0;
228 }
229 #endif
230