1 /* 2 * sbc8349.c -- WindRiver SBC8349 board support. 3 * Copyright (c) 2006-2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 * 26 */ 27 28 #include <common.h> 29 #include <ioports.h> 30 #include <mpc83xx.h> 31 #include <asm/mpc8349_pci.h> 32 #include <i2c.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #if defined(CONFIG_SPD_EEPROM) 36 #include <spd_sdram.h> 37 #endif 38 #if defined(CONFIG_OF_LIBFDT) 39 #include <libfdt.h> 40 #endif 41 42 int fixed_sdram(void); 43 void sdram_init(void); 44 45 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) 46 void ddr_enable_ecc(unsigned int dram_size); 47 #endif 48 49 #ifdef CONFIG_BOARD_EARLY_INIT_F 50 int board_early_init_f (void) 51 { 52 return 0; 53 } 54 #endif 55 56 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) 57 58 long int initdram (int board_type) 59 { 60 volatile immap_t *im = (immap_t *)CFG_IMMR; 61 u32 msize = 0; 62 63 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 64 return -1; 65 66 /* DDR SDRAM - Main SODIMM */ 67 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 68 #if defined(CONFIG_SPD_EEPROM) 69 msize = spd_sdram(); 70 #else 71 msize = fixed_sdram(); 72 #endif 73 /* 74 * Initialize SDRAM if it is on local bus. 75 */ 76 sdram_init(); 77 78 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 79 /* 80 * Initialize and enable DDR ECC. 81 */ 82 ddr_enable_ecc(msize * 1024 * 1024); 83 #endif 84 /* return total bus SDRAM size(bytes) -- DDR */ 85 return (msize * 1024 * 1024); 86 } 87 88 #if !defined(CONFIG_SPD_EEPROM) 89 /************************************************************************* 90 * fixed sdram init -- doesn't use serial presence detect. 91 ************************************************************************/ 92 int fixed_sdram(void) 93 { 94 volatile immap_t *im = (immap_t *)CFG_IMMR; 95 u32 msize = 0; 96 u32 ddr_size; 97 u32 ddr_size_log2; 98 99 msize = CFG_DDR_SIZE; 100 for (ddr_size = msize << 20, ddr_size_log2 = 0; 101 (ddr_size > 1); 102 ddr_size = ddr_size>>1, ddr_size_log2++) { 103 if (ddr_size & 1) { 104 return -1; 105 } 106 } 107 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); 108 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 109 110 #if (CFG_DDR_SIZE != 256) 111 #warning Currently any ddr size other than 256 is not supported 112 #endif 113 im->ddr.csbnds[2].csbnds = 0x0000000f; 114 im->ddr.cs_config[2] = CFG_DDR_CONFIG; 115 116 /* currently we use only one CS, so disable the other banks */ 117 im->ddr.cs_config[0] = 0; 118 im->ddr.cs_config[1] = 0; 119 im->ddr.cs_config[3] = 0; 120 121 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 122 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 123 124 im->ddr.sdram_cfg = 125 SDRAM_CFG_SREN 126 #if defined(CONFIG_DDR_2T_TIMING) 127 | SDRAM_CFG_2T_EN 128 #endif 129 | SDRAM_CFG_SDRAM_TYPE_DDR1; 130 #if defined (CONFIG_DDR_32BIT) 131 /* for 32-bit mode burst length is 8 */ 132 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); 133 #endif 134 im->ddr.sdram_mode = CFG_DDR_MODE; 135 136 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 137 udelay(200); 138 139 /* enable DDR controller */ 140 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 141 return msize; 142 } 143 #endif/*!CFG_SPD_EEPROM*/ 144 145 146 int checkboard (void) 147 { 148 puts("Board: Wind River SBC834x\n"); 149 return 0; 150 } 151 152 /* 153 * if board is fitted with SDRAM 154 */ 155 #if defined(CFG_BR2_PRELIM) \ 156 && defined(CFG_OR2_PRELIM) \ 157 && defined(CFG_LBLAWBAR2_PRELIM) \ 158 && defined(CFG_LBLAWAR2_PRELIM) 159 /* 160 * Initialize SDRAM memory on the Local Bus. 161 */ 162 163 void sdram_init(void) 164 { 165 volatile immap_t *immap = (immap_t *)CFG_IMMR; 166 volatile lbus83xx_t *lbc= &immap->lbus; 167 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 168 169 puts("\n SDRAM on Local Bus: "); 170 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 171 172 /* 173 * Setup SDRAM Base and Option Registers, already done in cpu_init.c 174 */ 175 176 /* setup mtrpt, lsrt and lbcr for LB bus */ 177 lbc->lbcr = CFG_LBC_LBCR; 178 lbc->mrtpr = CFG_LBC_MRTPR; 179 lbc->lsrt = CFG_LBC_LSRT; 180 asm("sync"); 181 182 /* 183 * Configure the SDRAM controller Machine Mode Register. 184 */ 185 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 186 187 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ 188 asm("sync"); 189 *sdram_addr = 0xff; 190 udelay(100); 191 192 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ 193 asm("sync"); 194 /*1 times*/ 195 *sdram_addr = 0xff; 196 udelay(100); 197 /*2 times*/ 198 *sdram_addr = 0xff; 199 udelay(100); 200 /*3 times*/ 201 *sdram_addr = 0xff; 202 udelay(100); 203 /*4 times*/ 204 *sdram_addr = 0xff; 205 udelay(100); 206 /*5 times*/ 207 *sdram_addr = 0xff; 208 udelay(100); 209 /*6 times*/ 210 *sdram_addr = 0xff; 211 udelay(100); 212 /*7 times*/ 213 *sdram_addr = 0xff; 214 udelay(100); 215 /*8 times*/ 216 *sdram_addr = 0xff; 217 udelay(100); 218 219 /* 0x58636733; mode register write operation */ 220 lbc->lsdmr = CFG_LBC_LSDMR_4; 221 asm("sync"); 222 *sdram_addr = 0xff; 223 udelay(100); 224 225 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ 226 asm("sync"); 227 *sdram_addr = 0xff; 228 udelay(100); 229 } 230 #else 231 void sdram_init(void) 232 { 233 puts(" SDRAM on Local Bus: Disabled in config\n"); 234 } 235 #endif 236 237 #if defined(CONFIG_OF_BOARD_SETUP) 238 void ft_board_setup(void *blob, bd_t *bd) 239 { 240 ft_cpu_setup(blob, bd); 241 #ifdef CONFIG_PCI 242 ft_pci_setup(blob, bd); 243 #endif 244 } 245 #endif 246