1*91e25769SPaul Gortmaker /* 2*91e25769SPaul Gortmaker * pci.c -- WindRiver SBC8349 PCI board support. 3*91e25769SPaul Gortmaker * Copyright (c) 2006 Wind River Systems, Inc. 4*91e25769SPaul Gortmaker * 5*91e25769SPaul Gortmaker * Based on MPC8349 PCI support but w/o PIB related code. 6*91e25769SPaul Gortmaker * 7*91e25769SPaul Gortmaker * See file CREDITS for list of people who contributed to this 8*91e25769SPaul Gortmaker * project. 9*91e25769SPaul Gortmaker * 10*91e25769SPaul Gortmaker * This program is free software; you can redistribute it and/or 11*91e25769SPaul Gortmaker * modify it under the terms of the GNU General Public License as 12*91e25769SPaul Gortmaker * published by the Free Software Foundation; either version 2 of 13*91e25769SPaul Gortmaker * the License, or (at your option) any later version. 14*91e25769SPaul Gortmaker * 15*91e25769SPaul Gortmaker * This program is distributed in the hope that it will be useful, 16*91e25769SPaul Gortmaker * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*91e25769SPaul Gortmaker * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*91e25769SPaul Gortmaker * GNU General Public License for more details. 19*91e25769SPaul Gortmaker * 20*91e25769SPaul Gortmaker * You should have received a copy of the GNU General Public License 21*91e25769SPaul Gortmaker * along with this program; if not, write to the Free Software 22*91e25769SPaul Gortmaker * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23*91e25769SPaul Gortmaker * MA 02111-1307 USA 24*91e25769SPaul Gortmaker * 25*91e25769SPaul Gortmaker */ 26*91e25769SPaul Gortmaker 27*91e25769SPaul Gortmaker #include <asm/mmu.h> 28*91e25769SPaul Gortmaker #include <common.h> 29*91e25769SPaul Gortmaker #include <asm/global_data.h> 30*91e25769SPaul Gortmaker #include <pci.h> 31*91e25769SPaul Gortmaker #include <asm/mpc8349_pci.h> 32*91e25769SPaul Gortmaker #include <i2c.h> 33*91e25769SPaul Gortmaker 34*91e25769SPaul Gortmaker DECLARE_GLOBAL_DATA_PTR; 35*91e25769SPaul Gortmaker 36*91e25769SPaul Gortmaker #ifdef CONFIG_PCI 37*91e25769SPaul Gortmaker 38*91e25769SPaul Gortmaker /* System RAM mapped to PCI space */ 39*91e25769SPaul Gortmaker #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE 40*91e25769SPaul Gortmaker #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE 41*91e25769SPaul Gortmaker 42*91e25769SPaul Gortmaker #ifndef CONFIG_PCI_PNP 43*91e25769SPaul Gortmaker static struct pci_config_table pci_mpc8349emds_config_table[] = { 44*91e25769SPaul Gortmaker {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 45*91e25769SPaul Gortmaker PCI_IDSEL_NUMBER, PCI_ANY_ID, 46*91e25769SPaul Gortmaker pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 47*91e25769SPaul Gortmaker PCI_ENET0_MEMADDR, 48*91e25769SPaul Gortmaker PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 49*91e25769SPaul Gortmaker } 50*91e25769SPaul Gortmaker }, 51*91e25769SPaul Gortmaker {} 52*91e25769SPaul Gortmaker }; 53*91e25769SPaul Gortmaker #endif 54*91e25769SPaul Gortmaker 55*91e25769SPaul Gortmaker static struct pci_controller pci_hose[] = { 56*91e25769SPaul Gortmaker { 57*91e25769SPaul Gortmaker #ifndef CONFIG_PCI_PNP 58*91e25769SPaul Gortmaker config_table:pci_mpc8349emds_config_table, 59*91e25769SPaul Gortmaker #endif 60*91e25769SPaul Gortmaker }, 61*91e25769SPaul Gortmaker { 62*91e25769SPaul Gortmaker #ifndef CONFIG_PCI_PNP 63*91e25769SPaul Gortmaker config_table:pci_mpc8349emds_config_table, 64*91e25769SPaul Gortmaker #endif 65*91e25769SPaul Gortmaker } 66*91e25769SPaul Gortmaker }; 67*91e25769SPaul Gortmaker 68*91e25769SPaul Gortmaker /************************************************************************** 69*91e25769SPaul Gortmaker * pci_init_board() 70*91e25769SPaul Gortmaker * 71*91e25769SPaul Gortmaker * NOTICE: PCI2 is not supported. There is only one 72*91e25769SPaul Gortmaker * physical PCI slot on the board. 73*91e25769SPaul Gortmaker * 74*91e25769SPaul Gortmaker */ 75*91e25769SPaul Gortmaker void 76*91e25769SPaul Gortmaker pci_init_board(void) 77*91e25769SPaul Gortmaker { 78*91e25769SPaul Gortmaker volatile immap_t * immr; 79*91e25769SPaul Gortmaker volatile clk83xx_t * clk; 80*91e25769SPaul Gortmaker volatile law83xx_t * pci_law; 81*91e25769SPaul Gortmaker volatile pot83xx_t * pci_pot; 82*91e25769SPaul Gortmaker volatile pcictrl83xx_t * pci_ctrl; 83*91e25769SPaul Gortmaker volatile pciconf83xx_t * pci_conf; 84*91e25769SPaul Gortmaker u16 reg16; 85*91e25769SPaul Gortmaker u32 reg32; 86*91e25769SPaul Gortmaker u32 dev; 87*91e25769SPaul Gortmaker struct pci_controller * hose; 88*91e25769SPaul Gortmaker 89*91e25769SPaul Gortmaker immr = (immap_t *)CFG_IMMR; 90*91e25769SPaul Gortmaker clk = (clk83xx_t *)&immr->clk; 91*91e25769SPaul Gortmaker pci_law = immr->sysconf.pcilaw; 92*91e25769SPaul Gortmaker pci_pot = immr->ios.pot; 93*91e25769SPaul Gortmaker pci_ctrl = immr->pci_ctrl; 94*91e25769SPaul Gortmaker pci_conf = immr->pci_conf; 95*91e25769SPaul Gortmaker 96*91e25769SPaul Gortmaker hose = &pci_hose[0]; 97*91e25769SPaul Gortmaker 98*91e25769SPaul Gortmaker /* 99*91e25769SPaul Gortmaker * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode 100*91e25769SPaul Gortmaker */ 101*91e25769SPaul Gortmaker 102*91e25769SPaul Gortmaker reg32 = clk->occr; 103*91e25769SPaul Gortmaker udelay(2000); 104*91e25769SPaul Gortmaker clk->occr = 0xff000000; 105*91e25769SPaul Gortmaker udelay(2000); 106*91e25769SPaul Gortmaker 107*91e25769SPaul Gortmaker /* 108*91e25769SPaul Gortmaker * Release PCI RST Output signal 109*91e25769SPaul Gortmaker */ 110*91e25769SPaul Gortmaker pci_ctrl[0].gcr = 0; 111*91e25769SPaul Gortmaker udelay(2000); 112*91e25769SPaul Gortmaker pci_ctrl[0].gcr = 1; 113*91e25769SPaul Gortmaker 114*91e25769SPaul Gortmaker #ifdef CONFIG_MPC83XX_PCI2 115*91e25769SPaul Gortmaker pci_ctrl[1].gcr = 0; 116*91e25769SPaul Gortmaker udelay(2000); 117*91e25769SPaul Gortmaker pci_ctrl[1].gcr = 1; 118*91e25769SPaul Gortmaker #endif 119*91e25769SPaul Gortmaker 120*91e25769SPaul Gortmaker /* We need to wait at least a 1sec based on PCI specs */ 121*91e25769SPaul Gortmaker { 122*91e25769SPaul Gortmaker int i; 123*91e25769SPaul Gortmaker 124*91e25769SPaul Gortmaker for (i = 0; i < 1000; ++i) 125*91e25769SPaul Gortmaker udelay (1000); 126*91e25769SPaul Gortmaker } 127*91e25769SPaul Gortmaker 128*91e25769SPaul Gortmaker /* 129*91e25769SPaul Gortmaker * Configure PCI Local Access Windows 130*91e25769SPaul Gortmaker */ 131*91e25769SPaul Gortmaker pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; 132*91e25769SPaul Gortmaker pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 133*91e25769SPaul Gortmaker 134*91e25769SPaul Gortmaker pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; 135*91e25769SPaul Gortmaker pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 136*91e25769SPaul Gortmaker 137*91e25769SPaul Gortmaker /* 138*91e25769SPaul Gortmaker * Configure PCI Outbound Translation Windows 139*91e25769SPaul Gortmaker */ 140*91e25769SPaul Gortmaker 141*91e25769SPaul Gortmaker /* PCI1 mem space - prefetch */ 142*91e25769SPaul Gortmaker pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; 143*91e25769SPaul Gortmaker pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; 144*91e25769SPaul Gortmaker pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); 145*91e25769SPaul Gortmaker 146*91e25769SPaul Gortmaker /* PCI1 IO space */ 147*91e25769SPaul Gortmaker pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; 148*91e25769SPaul Gortmaker pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; 149*91e25769SPaul Gortmaker pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); 150*91e25769SPaul Gortmaker 151*91e25769SPaul Gortmaker /* PCI1 mmio - non-prefetch mem space */ 152*91e25769SPaul Gortmaker pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; 153*91e25769SPaul Gortmaker pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; 154*91e25769SPaul Gortmaker pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); 155*91e25769SPaul Gortmaker 156*91e25769SPaul Gortmaker /* 157*91e25769SPaul Gortmaker * Configure PCI Inbound Translation Windows 158*91e25769SPaul Gortmaker */ 159*91e25769SPaul Gortmaker 160*91e25769SPaul Gortmaker /* we need RAM mapped to PCI space for the devices to 161*91e25769SPaul Gortmaker * access main memory */ 162*91e25769SPaul Gortmaker pci_ctrl[0].pitar1 = 0x0; 163*91e25769SPaul Gortmaker pci_ctrl[0].pibar1 = 0x0; 164*91e25769SPaul Gortmaker pci_ctrl[0].piebar1 = 0x0; 165*91e25769SPaul Gortmaker pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); 166*91e25769SPaul Gortmaker 167*91e25769SPaul Gortmaker hose->first_busno = 0; 168*91e25769SPaul Gortmaker hose->last_busno = 0xff; 169*91e25769SPaul Gortmaker 170*91e25769SPaul Gortmaker /* PCI memory prefetch space */ 171*91e25769SPaul Gortmaker pci_set_region(hose->regions + 0, 172*91e25769SPaul Gortmaker CFG_PCI1_MEM_BASE, 173*91e25769SPaul Gortmaker CFG_PCI1_MEM_PHYS, 174*91e25769SPaul Gortmaker CFG_PCI1_MEM_SIZE, 175*91e25769SPaul Gortmaker PCI_REGION_MEM|PCI_REGION_PREFETCH); 176*91e25769SPaul Gortmaker 177*91e25769SPaul Gortmaker /* PCI memory space */ 178*91e25769SPaul Gortmaker pci_set_region(hose->regions + 1, 179*91e25769SPaul Gortmaker CFG_PCI1_MMIO_BASE, 180*91e25769SPaul Gortmaker CFG_PCI1_MMIO_PHYS, 181*91e25769SPaul Gortmaker CFG_PCI1_MMIO_SIZE, 182*91e25769SPaul Gortmaker PCI_REGION_MEM); 183*91e25769SPaul Gortmaker 184*91e25769SPaul Gortmaker /* PCI IO space */ 185*91e25769SPaul Gortmaker pci_set_region(hose->regions + 2, 186*91e25769SPaul Gortmaker CFG_PCI1_IO_BASE, 187*91e25769SPaul Gortmaker CFG_PCI1_IO_PHYS, 188*91e25769SPaul Gortmaker CFG_PCI1_IO_SIZE, 189*91e25769SPaul Gortmaker PCI_REGION_IO); 190*91e25769SPaul Gortmaker 191*91e25769SPaul Gortmaker /* System memory space */ 192*91e25769SPaul Gortmaker pci_set_region(hose->regions + 3, 193*91e25769SPaul Gortmaker CONFIG_PCI_SYS_MEM_BUS, 194*91e25769SPaul Gortmaker CONFIG_PCI_SYS_MEM_PHYS, 195*91e25769SPaul Gortmaker gd->ram_size, 196*91e25769SPaul Gortmaker PCI_REGION_MEM | PCI_REGION_MEMORY); 197*91e25769SPaul Gortmaker 198*91e25769SPaul Gortmaker hose->region_count = 4; 199*91e25769SPaul Gortmaker 200*91e25769SPaul Gortmaker pci_setup_indirect(hose, 201*91e25769SPaul Gortmaker (CFG_IMMR+0x8300), 202*91e25769SPaul Gortmaker (CFG_IMMR+0x8304)); 203*91e25769SPaul Gortmaker 204*91e25769SPaul Gortmaker pci_register_hose(hose); 205*91e25769SPaul Gortmaker 206*91e25769SPaul Gortmaker /* 207*91e25769SPaul Gortmaker * Write to Command register 208*91e25769SPaul Gortmaker */ 209*91e25769SPaul Gortmaker reg16 = 0xff; 210*91e25769SPaul Gortmaker dev = PCI_BDF(hose->first_busno, 0, 0); 211*91e25769SPaul Gortmaker pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 212*91e25769SPaul Gortmaker reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 213*91e25769SPaul Gortmaker pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 214*91e25769SPaul Gortmaker 215*91e25769SPaul Gortmaker /* 216*91e25769SPaul Gortmaker * Clear non-reserved bits in status register. 217*91e25769SPaul Gortmaker */ 218*91e25769SPaul Gortmaker pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 219*91e25769SPaul Gortmaker pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 220*91e25769SPaul Gortmaker pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 221*91e25769SPaul Gortmaker 222*91e25769SPaul Gortmaker #ifdef CONFIG_PCI_SCAN_SHOW 223*91e25769SPaul Gortmaker printf("PCI: Bus Dev VenId DevId Class Int\n"); 224*91e25769SPaul Gortmaker #endif 225*91e25769SPaul Gortmaker /* 226*91e25769SPaul Gortmaker * Hose scan. 227*91e25769SPaul Gortmaker */ 228*91e25769SPaul Gortmaker hose->last_busno = pci_hose_scan(hose); 229*91e25769SPaul Gortmaker 230*91e25769SPaul Gortmaker #ifdef CONFIG_MPC83XX_PCI2 231*91e25769SPaul Gortmaker hose = &pci_hose[1]; 232*91e25769SPaul Gortmaker 233*91e25769SPaul Gortmaker /* 234*91e25769SPaul Gortmaker * Configure PCI Outbound Translation Windows 235*91e25769SPaul Gortmaker */ 236*91e25769SPaul Gortmaker 237*91e25769SPaul Gortmaker /* PCI2 mem space - prefetch */ 238*91e25769SPaul Gortmaker pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; 239*91e25769SPaul Gortmaker pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; 240*91e25769SPaul Gortmaker pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); 241*91e25769SPaul Gortmaker 242*91e25769SPaul Gortmaker /* PCI2 IO space */ 243*91e25769SPaul Gortmaker pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; 244*91e25769SPaul Gortmaker pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; 245*91e25769SPaul Gortmaker pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); 246*91e25769SPaul Gortmaker 247*91e25769SPaul Gortmaker /* PCI2 mmio - non-prefetch mem space */ 248*91e25769SPaul Gortmaker pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; 249*91e25769SPaul Gortmaker pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; 250*91e25769SPaul Gortmaker pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); 251*91e25769SPaul Gortmaker 252*91e25769SPaul Gortmaker /* 253*91e25769SPaul Gortmaker * Configure PCI Inbound Translation Windows 254*91e25769SPaul Gortmaker */ 255*91e25769SPaul Gortmaker 256*91e25769SPaul Gortmaker /* we need RAM mapped to PCI space for the devices to 257*91e25769SPaul Gortmaker * access main memory */ 258*91e25769SPaul Gortmaker pci_ctrl[1].pitar1 = 0x0; 259*91e25769SPaul Gortmaker pci_ctrl[1].pibar1 = 0x0; 260*91e25769SPaul Gortmaker pci_ctrl[1].piebar1 = 0x0; 261*91e25769SPaul Gortmaker pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); 262*91e25769SPaul Gortmaker 263*91e25769SPaul Gortmaker hose->first_busno = pci_hose[0].last_busno + 1; 264*91e25769SPaul Gortmaker hose->last_busno = 0xff; 265*91e25769SPaul Gortmaker 266*91e25769SPaul Gortmaker /* PCI memory prefetch space */ 267*91e25769SPaul Gortmaker pci_set_region(hose->regions + 0, 268*91e25769SPaul Gortmaker CFG_PCI2_MEM_BASE, 269*91e25769SPaul Gortmaker CFG_PCI2_MEM_PHYS, 270*91e25769SPaul Gortmaker CFG_PCI2_MEM_SIZE, 271*91e25769SPaul Gortmaker PCI_REGION_MEM|PCI_REGION_PREFETCH); 272*91e25769SPaul Gortmaker 273*91e25769SPaul Gortmaker /* PCI memory space */ 274*91e25769SPaul Gortmaker pci_set_region(hose->regions + 1, 275*91e25769SPaul Gortmaker CFG_PCI2_MMIO_BASE, 276*91e25769SPaul Gortmaker CFG_PCI2_MMIO_PHYS, 277*91e25769SPaul Gortmaker CFG_PCI2_MMIO_SIZE, 278*91e25769SPaul Gortmaker PCI_REGION_MEM); 279*91e25769SPaul Gortmaker 280*91e25769SPaul Gortmaker /* PCI IO space */ 281*91e25769SPaul Gortmaker pci_set_region(hose->regions + 2, 282*91e25769SPaul Gortmaker CFG_PCI2_IO_BASE, 283*91e25769SPaul Gortmaker CFG_PCI2_IO_PHYS, 284*91e25769SPaul Gortmaker CFG_PCI2_IO_SIZE, 285*91e25769SPaul Gortmaker PCI_REGION_IO); 286*91e25769SPaul Gortmaker 287*91e25769SPaul Gortmaker /* System memory space */ 288*91e25769SPaul Gortmaker pci_set_region(hose->regions + 3, 289*91e25769SPaul Gortmaker CONFIG_PCI_SYS_MEM_BUS, 290*91e25769SPaul Gortmaker CONFIG_PCI_SYS_MEM_PHYS, 291*91e25769SPaul Gortmaker gd->ram_size, 292*91e25769SPaul Gortmaker PCI_REGION_MEM | PCI_REGION_MEMORY); 293*91e25769SPaul Gortmaker 294*91e25769SPaul Gortmaker hose->region_count = 4; 295*91e25769SPaul Gortmaker 296*91e25769SPaul Gortmaker pci_setup_indirect(hose, 297*91e25769SPaul Gortmaker (CFG_IMMR+0x8380), 298*91e25769SPaul Gortmaker (CFG_IMMR+0x8384)); 299*91e25769SPaul Gortmaker 300*91e25769SPaul Gortmaker pci_register_hose(hose); 301*91e25769SPaul Gortmaker 302*91e25769SPaul Gortmaker /* 303*91e25769SPaul Gortmaker * Write to Command register 304*91e25769SPaul Gortmaker */ 305*91e25769SPaul Gortmaker reg16 = 0xff; 306*91e25769SPaul Gortmaker dev = PCI_BDF(hose->first_busno, 0, 0); 307*91e25769SPaul Gortmaker pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 308*91e25769SPaul Gortmaker reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 309*91e25769SPaul Gortmaker pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 310*91e25769SPaul Gortmaker 311*91e25769SPaul Gortmaker /* 312*91e25769SPaul Gortmaker * Clear non-reserved bits in status register. 313*91e25769SPaul Gortmaker */ 314*91e25769SPaul Gortmaker pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 315*91e25769SPaul Gortmaker pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 316*91e25769SPaul Gortmaker pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 317*91e25769SPaul Gortmaker 318*91e25769SPaul Gortmaker /* 319*91e25769SPaul Gortmaker * Hose scan. 320*91e25769SPaul Gortmaker */ 321*91e25769SPaul Gortmaker hose->last_busno = pci_hose_scan(hose); 322*91e25769SPaul Gortmaker #endif 323*91e25769SPaul Gortmaker 324*91e25769SPaul Gortmaker } 325*91e25769SPaul Gortmaker 326*91e25769SPaul Gortmaker #ifdef CONFIG_OF_FLAT_TREE 327*91e25769SPaul Gortmaker void 328*91e25769SPaul Gortmaker ft_pci_setup(void *blob, bd_t *bd) 329*91e25769SPaul Gortmaker { 330*91e25769SPaul Gortmaker u32 *p; 331*91e25769SPaul Gortmaker int len; 332*91e25769SPaul Gortmaker 333*91e25769SPaul Gortmaker p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); 334*91e25769SPaul Gortmaker if (p != NULL) { 335*91e25769SPaul Gortmaker p[0] = pci_hose[0].first_busno; 336*91e25769SPaul Gortmaker p[1] = pci_hose[0].last_busno; 337*91e25769SPaul Gortmaker } 338*91e25769SPaul Gortmaker 339*91e25769SPaul Gortmaker #ifdef CONFIG_MPC83XX_PCI2 340*91e25769SPaul Gortmaker p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); 341*91e25769SPaul Gortmaker if (p != NULL) { 342*91e25769SPaul Gortmaker p[0] = pci_hose[1].first_busno; 343*91e25769SPaul Gortmaker p[1] = pci_hose[1].last_busno; 344*91e25769SPaul Gortmaker } 345*91e25769SPaul Gortmaker #endif 346*91e25769SPaul Gortmaker } 347*91e25769SPaul Gortmaker #endif /* CONFIG_OF_FLAT_TREE */ 348*91e25769SPaul Gortmaker #endif /* CONFIG_PCI */ 349