1 /* 2 * Copyright (C) 2016 samtec automotive software & electronics gmbh 3 * 4 * Author: Christoph Fritz <chf.fritz@googlemail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/gpio.h> 16 #include <asm/mach-imx/iomux-v3.h> 17 #include <asm/io.h> 18 #include <asm/mach-imx/mxc_i2c.h> 19 #include <linux/sizes.h> 20 #include <common.h> 21 #include <environment.h> 22 #include <fsl_esdhc.h> 23 #include <mmc.h> 24 #include <i2c.h> 25 #include <miiphy.h> 26 #include <netdev.h> 27 #include <power/pmic.h> 28 #include <power/pfuze100_pmic.h> 29 #include <usb.h> 30 #include <usb/ehci-ci.h> 31 #include <pwm.h> 32 #include <wait_bit.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ 37 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 38 PAD_CTL_SRE_FAST) 39 40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \ 41 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ 42 PAD_CTL_SRE_FAST) 43 44 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm 45 46 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \ 47 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \ 48 PAD_CTL_SRE_FAST) 49 50 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ 51 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \ 52 PAD_CTL_DSE_40ohm) 53 54 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 55 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST) 56 57 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 58 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \ 59 PAD_CTL_SRE_FAST) 60 61 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ 62 PAD_CTL_PKE) 63 64 int dram_init(void) 65 { 66 gd->ram_size = imx_ddr_size(); 67 68 return 0; 69 } 70 71 static iomux_v3_cfg_t const uart1_pads[] = { 72 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 73 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 74 }; 75 76 static iomux_v3_cfg_t const usdhc2_pads[] = { 77 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), 78 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL), 84 }; 85 86 static iomux_v3_cfg_t const usdhc4_pads[] = { 87 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), 88 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 95 MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 96 MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 97 }; 98 99 static iomux_v3_cfg_t const fec1_pads[] = { 100 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 103 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 104 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 105 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 107 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 108 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) | 109 MUX_MODE_SION, 110 /* LAN8720 PHY Reset */ 111 MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL), 112 }; 113 114 static iomux_v3_cfg_t const pwm_led_pads[] = { 115 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */ 116 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */ 117 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */ 118 }; 119 120 static void setup_iomux_uart(void) 121 { 122 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 123 } 124 125 #define PHY_RESET IMX_GPIO_NR(5, 9) 126 127 int board_eth_init(bd_t *bis) 128 { 129 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 130 int ret; 131 unsigned char eth1addr[6]; 132 133 /* just to get secound mac address */ 134 imx_get_mac_from_fuse(1, eth1addr); 135 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) 136 eth_env_set_enetaddr("eth1addr", eth1addr); 137 138 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 139 140 /* 141 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing 142 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by 143 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver. 144 */ 145 clrsetbits_le32(&iomuxc_regs->gpr[1], 146 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK | 147 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, 148 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK | 149 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 150 151 ret = enable_fec_anatop_clock(0, ENET_50MHZ); 152 if (ret) 153 goto eth_fail; 154 155 /* reset phy */ 156 gpio_direction_output(PHY_RESET, 0); 157 mdelay(16); 158 gpio_set_value(PHY_RESET, 1); 159 mdelay(1); 160 161 ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR, 162 IMX_FEC_BASE); 163 if (ret) 164 goto eth_fail; 165 166 return ret; 167 168 eth_fail: 169 printf("FEC MXC: %s:failed (%i)\n", __func__, ret); 170 gpio_set_value(PHY_RESET, 0); 171 return ret; 172 } 173 174 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 175 /* I2C1 for PMIC */ 176 static struct i2c_pads_info i2c_pad_info1 = { 177 .scl = { 178 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, 179 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, 180 .gp = IMX_GPIO_NR(1, 0), 181 }, 182 .sda = { 183 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, 184 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, 185 .gp = IMX_GPIO_NR(1, 1), 186 }, 187 }; 188 189 static struct pmic *pfuze_init(unsigned char i2cbus) 190 { 191 struct pmic *p; 192 int ret; 193 u32 reg; 194 195 ret = power_pfuze100_init(i2cbus); 196 if (ret) 197 return NULL; 198 199 p = pmic_get("PFUZE100"); 200 ret = pmic_probe(p); 201 if (ret) 202 return NULL; 203 204 pmic_reg_read(p, PFUZE100_DEVICEID, ®); 205 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 206 207 /* Set SW1AB stanby volage to 0.975V */ 208 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); 209 reg &= ~SW1x_STBY_MASK; 210 reg |= SW1x_0_975V; 211 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); 212 213 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 214 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); 215 reg &= ~SW1xCONF_DVSSPEED_MASK; 216 reg |= SW1xCONF_DVSSPEED_4US; 217 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); 218 219 /* Set SW1C standby voltage to 0.975V */ 220 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); 221 reg &= ~SW1x_STBY_MASK; 222 reg |= SW1x_0_975V; 223 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); 224 225 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ 226 pmic_reg_read(p, PFUZE100_SW1CCONF, ®); 227 reg &= ~SW1xCONF_DVSSPEED_MASK; 228 reg |= SW1xCONF_DVSSPEED_4US; 229 pmic_reg_write(p, PFUZE100_SW1CCONF, reg); 230 231 return p; 232 } 233 234 static int pfuze_mode_init(struct pmic *p, u32 mode) 235 { 236 unsigned char offset, i, switch_num; 237 u32 id; 238 int ret; 239 240 pmic_reg_read(p, PFUZE100_DEVICEID, &id); 241 id = id & 0xf; 242 243 if (id == 0) { 244 switch_num = 6; 245 offset = PFUZE100_SW1CMODE; 246 } else if (id == 1) { 247 switch_num = 4; 248 offset = PFUZE100_SW2MODE; 249 } else { 250 printf("Not supported, id=%d\n", id); 251 return -EINVAL; 252 } 253 254 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); 255 if (ret < 0) { 256 printf("Set SW1AB mode error!\n"); 257 return ret; 258 } 259 260 for (i = 0; i < switch_num - 1; i++) { 261 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); 262 if (ret < 0) { 263 printf("Set switch 0x%x mode error!\n", 264 offset + i * SWITCH_SIZE); 265 return ret; 266 } 267 } 268 269 return ret; 270 } 271 272 int power_init_board(void) 273 { 274 struct pmic *p; 275 int ret; 276 277 p = pfuze_init(I2C_PMIC); 278 if (!p) 279 return -ENODEV; 280 281 ret = pfuze_mode_init(p, APS_PFM); 282 if (ret < 0) 283 return ret; 284 285 return 0; 286 } 287 288 #ifdef CONFIG_USB_EHCI_MX6 289 static iomux_v3_cfg_t const usb_otg_pads[] = { 290 /* OGT1 */ 291 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 292 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 293 /* OTG2 */ 294 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) 295 }; 296 297 static void setup_iomux_usb(void) 298 { 299 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 300 ARRAY_SIZE(usb_otg_pads)); 301 } 302 303 int board_usb_phy_mode(int port) 304 { 305 if (port == 1) 306 return USB_INIT_HOST; 307 else 308 return usb_phy_mode(port); 309 } 310 #endif 311 312 #ifdef CONFIG_PWM_IMX 313 static int set_pwm_leds(void) 314 { 315 int ret; 316 317 imx_iomux_v3_setup_multiple_pads(pwm_led_pads, 318 ARRAY_SIZE(pwm_led_pads)); 319 /* enable backlight PWM 2, green LED */ 320 ret = pwm_init(1, 0, 0); 321 if (ret) 322 goto error; 323 /* duty cycle 200ns, period: 8000ns */ 324 ret = pwm_config(1, 200, 8000); 325 if (ret) 326 goto error; 327 ret = pwm_enable(1); 328 if (ret) 329 goto error; 330 331 /* enable backlight PWM 1, blue LED */ 332 ret = pwm_init(0, 0, 0); 333 if (ret) 334 goto error; 335 /* duty cycle 200ns, period: 8000ns */ 336 ret = pwm_config(0, 200, 8000); 337 if (ret) 338 goto error; 339 ret = pwm_enable(0); 340 if (ret) 341 goto error; 342 343 /* enable backlight PWM 6, red LED */ 344 ret = pwm_init(5, 0, 0); 345 if (ret) 346 goto error; 347 /* duty cycle 200ns, period: 8000ns */ 348 ret = pwm_config(5, 200, 8000); 349 if (ret) 350 goto error; 351 ret = pwm_enable(5); 352 353 error: 354 return ret; 355 } 356 #else 357 static int set_pwm_leds(void) 358 { 359 return 0; 360 } 361 #endif 362 363 #define ADCx_HC0 0x00 364 #define ADCx_HS 0x08 365 #define ADCx_HS_C0 BIT(0) 366 #define ADCx_R0 0x0c 367 #define ADCx_CFG 0x14 368 #define ADCx_CFG_SWMODE 0x308 369 #define ADCx_GC 0x18 370 #define ADCx_GC_CAL BIT(7) 371 372 static int read_adc(u32 *val) 373 { 374 int ret; 375 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE); 376 377 /* use software mode */ 378 writel(ADCx_CFG_SWMODE, b + ADCx_CFG); 379 380 /* start auto calibration */ 381 setbits_le32(b + ADCx_GC, ADCx_GC_CAL); 382 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0); 383 if (ret) 384 goto adc_exit; 385 386 /* start conversion */ 387 writel(0, b + ADCx_HC0); 388 389 /* wait for conversion */ 390 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0); 391 if (ret) 392 goto adc_exit; 393 394 /* read result */ 395 *val = readl(b + ADCx_R0); 396 397 adc_exit: 398 if (ret) 399 printf("ADC failure (ret=%i)\n", ret); 400 unmap_physmem(b, MAP_NOCACHE); 401 return ret; 402 } 403 404 #define VAL_UPPER 2498 405 #define VAL_LOWER 1550 406 407 static int set_pin_state(void) 408 { 409 u32 val; 410 int ret; 411 412 ret = read_adc(&val); 413 if (ret) 414 return ret; 415 416 if (val >= VAL_UPPER) 417 env_set("pin_state", "connected"); 418 else if (val < VAL_UPPER && val > VAL_LOWER) 419 env_set("pin_state", "open"); 420 else 421 env_set("pin_state", "button"); 422 423 return ret; 424 } 425 426 int board_late_init(void) 427 { 428 int ret; 429 430 ret = set_pwm_leds(); 431 if (ret) 432 return ret; 433 434 ret = set_pin_state(); 435 436 return ret; 437 } 438 439 int board_early_init_f(void) 440 { 441 setup_iomux_uart(); 442 443 setup_iomux_usb(); 444 445 return 0; 446 } 447 448 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 449 {USDHC4_BASE_ADDR, 0, 8}, 450 {USDHC2_BASE_ADDR, 0, 4}, 451 }; 452 453 #define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28) 454 455 int board_mmc_getcd(struct mmc *mmc) 456 { 457 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 458 459 if (cfg->esdhc_base == USDHC4_BASE_ADDR) 460 return 1; 461 if (cfg->esdhc_base == USDHC2_BASE_ADDR) 462 return !gpio_get_value(USDHC2_CD_GPIO); 463 464 return -EINVAL; 465 } 466 467 int board_mmc_init(bd_t *bis) 468 { 469 int ret; 470 471 /* 472 * According to the board_mmc_init() the following map is done: 473 * (U-Boot device node) (Physical Port) 474 * mmc0 USDHC4 475 * mmc1 USDHC2 476 */ 477 imx_iomux_v3_setup_multiple_pads( 478 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 479 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 480 481 imx_iomux_v3_setup_multiple_pads( 482 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 483 gpio_direction_input(USDHC2_CD_GPIO); 484 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 485 486 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 487 if (ret) { 488 printf("Warning: failed to initialize USDHC4\n"); 489 return ret; 490 } 491 492 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]); 493 if (ret) { 494 printf("Warning: failed to initialize USDHC2\n"); 495 return ret; 496 } 497 498 return 0; 499 } 500 501 int board_init(void) 502 { 503 /* Address of boot parameters */ 504 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 505 506 #ifdef CONFIG_SYS_I2C_MXC 507 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 508 #endif 509 510 return 0; 511 } 512 513 int checkboard(void) 514 { 515 puts("Board: VIN|ING 2000\n"); 516 517 return 0; 518 } 519