1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 */
5
6#define __ASSEMBLY__
7#include <config.h>
8
9/* image version */
10
11IMAGE_VERSION 2
12
13/*
14 * Boot Device : one of
15 * spi/sd/nand/onenand, qspi/nor
16 */
17
18BOOT_FROM	sd
19
20/*
21 * Device Configuration Data (DCD)
22 *
23 * Each entry must have the format:
24 * Addr-type           Address        Value
25 *
26 * where:
27 *	Addr-type register length (1,2 or 4 bytes)
28 *	Address	  absolute address of the register
29 *	value	  value to be stored in the register
30 */
31
32/* Enable all clocks */
33DATA 4 0x020c4068 0xffffffff
34DATA 4 0x020c406c 0xffffffff
35DATA 4 0x020c4070 0xffffffff
36DATA 4 0x020c4074 0xffffffff
37DATA 4 0x020c4078 0xffffffff
38DATA 4 0x020c407c 0xffffffff
39DATA 4 0x020c4080 0xffffffff
40DATA 4 0x020c4084 0xffffffff
41
42/* IOMUX - DDR IO Type */
43DATA 4 0x020e0618 0x000c0000
44DATA 4 0x020e05fc 0x00000000
45
46/* Clock */
47DATA 4 0x020e032c 0x00000030
48
49/* Address */
50DATA 4 0x020e0300 0x00000028
51DATA 4 0x020e02fc 0x00000028
52DATA 4 0x020e05f4 0x00000028
53
54/* Control */
55DATA 4 0x020e0340 0x00000028
56
57DATA 4 0x020e0320 0x00000000
58DATA 4 0x020e0310 0x00000028
59DATA 4 0x020e0314 0x00000028
60DATA 4 0x020e0614 0x00000028
61
62/* Data Strobe */
63DATA 4 0x020e05f8 0x00020000
64DATA 4 0x020e0330 0x00000028
65DATA 4 0x020e0334 0x00000028
66DATA 4 0x020e0338 0x00000028
67DATA 4 0x020e033c 0x00000028
68
69/* Data */
70DATA 4 0x020e0608 0x00020000
71DATA 4 0x020e060c 0x00000028
72DATA 4 0x020e0610 0x00000028
73DATA 4 0x020e061c 0x00000028
74DATA 4 0x020e0620 0x00000028
75DATA 4 0x020e02ec 0x00000028
76DATA 4 0x020e02f0 0x00000028
77DATA 4 0x020e02f4 0x00000028
78DATA 4 0x020e02f8 0x00000028
79
80/* Calibrations - ZQ */
81DATA 4 0x021b0800 0xa1390003
82
83/* Write leveling */
84DATA 4 0x021b080c 0x00290025
85DATA 4 0x021b0810 0x00210022
86
87/* DQS Read Gate */
88DATA 4 0x021b083c 0x4142013a
89DATA 4 0x021b0840 0x012e0123
90
91/* Read/Write Delay */
92DATA 4 0x021b0848 0x43474949
93DATA 4 0x021b0850 0x38383c38
94
95/* Read data bit delay */
96DATA 4 0x021b081c 0x33333333
97DATA 4 0x021b0820 0x33333333
98DATA 4 0x021b0824 0x33333333
99DATA 4 0x021b0828 0x33333333
100
101/* Complete calibration by forced measurement */
102DATA 4 0x021b08b8 0x00000800
103
104/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
105DATA 4 0x021b0004 0x0002002d
106DATA 4 0x021b0008 0x00333040
107DATA 4 0x021b000c 0x676b52f2
108DATA 4 0x021b0010 0x926e8b63
109DATA 4 0x021b0014 0x01ff00db
110DATA 4 0x021b0018 0x00011740
111DATA 4 0x021b001c 0x00008000
112DATA 4 0x021b002c 0x000026d2
113DATA 4 0x021b0030 0x006b1023
114DATA 4 0x021b0040 0x0000005f
115DATA 4 0x021b0000 0x84190000
116
117/* Initialize MT41K256M16HA-125 - MR2 */
118DATA 4 0x021b001c 0x02008032
119/* MR3 */
120DATA 4 0x021b001c 0x00008033
121/* MR1 */
122DATA 4 0x021b001c 0x00048031
123/* MR0 */
124DATA 4 0x021b001c 0x15108030
125/* DDR device ZQ calibration */
126DATA 4 0x021b001c 0x04008040
127
128/* Final DDR setup, before operation start */
129DATA 4 0x021b0020 0x00007800
130DATA 4 0x021b0818 0x00022227
131DATA 4 0x021b001c 0x00000000
132