1 /* 2 * Copyright (C) 2010 Samsung Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <spi.h> 27 #include <lcd.h> 28 #include <asm/io.h> 29 #include <asm/gpio.h> 30 #include <asm/arch/adc.h> 31 #include <asm/arch/gpio.h> 32 #include <asm/arch/mmc.h> 33 #include <asm/arch/pinmux.h> 34 #include <pmic.h> 35 #include <usb/s3c_udc.h> 36 #include <asm/arch/cpu.h> 37 #include <max8998_pmic.h> 38 #include <asm/arch/watchdog.h> 39 #include <libtizen.h> 40 #include <ld9040.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 struct exynos4_gpio_part1 *gpio1; 45 struct exynos4_gpio_part2 *gpio2; 46 unsigned int board_rev; 47 48 u32 get_board_rev(void) 49 { 50 return board_rev; 51 } 52 53 static int get_hwrev(void) 54 { 55 return board_rev & 0xFF; 56 } 57 58 static void check_hw_revision(void); 59 60 int dram_init(void) 61 { 62 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 63 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 64 65 return 0; 66 } 67 68 void dram_init_banksize(void) 69 { 70 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 71 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 72 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 73 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 74 } 75 76 static unsigned short get_adc_value(int channel) 77 { 78 struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); 79 unsigned short ret = 0; 80 unsigned int reg; 81 unsigned int loop = 0; 82 83 writel(channel & 0xF, &adc->adcmux); 84 writel((1 << 14) | (49 << 6), &adc->adccon); 85 writel(1000 & 0xffff, &adc->adcdly); 86 writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */ 87 udelay(10); 88 writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */ 89 udelay(10); 90 91 do { 92 udelay(1); 93 reg = readl(&adc->adccon); 94 } while (!(reg & (1 << 15)) && (loop++ < 1000)); 95 96 ret = readl(&adc->adcdat0) & 0xFFF; 97 98 return ret; 99 } 100 101 static int adc_power_control(int on) 102 { 103 int ret; 104 struct pmic *p = get_pmic(); 105 106 if (pmic_probe(p)) 107 return -1; 108 109 ret = pmic_set_output(p, 110 MAX8998_REG_ONOFF1, 111 MAX8998_LDO4, !!on); 112 113 return ret; 114 } 115 116 static unsigned int get_hw_revision(void) 117 { 118 int hwrev, mode0, mode1; 119 120 adc_power_control(1); 121 122 mode0 = get_adc_value(1); /* HWREV_MODE0 */ 123 mode1 = get_adc_value(2); /* HWREV_MODE1 */ 124 125 /* 126 * XXX Always set the default hwrev as the latest board 127 * ADC = (voltage) / 3.3 * 4096 128 */ 129 hwrev = 3; 130 131 #define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max)) 132 if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200)) 133 hwrev = 0x0; /* 0.01V 0.01V */ 134 if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200)) 135 hwrev = 0x1; /* 610mV 0.01V */ 136 if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200)) 137 hwrev = 0x2; /* 1.16V 0.01V */ 138 if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200)) 139 hwrev = 0x3; /* 1.79V 0.01V */ 140 #undef IS_RANGE 141 142 debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev); 143 144 adc_power_control(0); 145 146 return hwrev; 147 } 148 149 static void check_hw_revision(void) 150 { 151 int hwrev; 152 153 hwrev = get_hw_revision(); 154 155 board_rev |= hwrev; 156 } 157 158 #ifdef CONFIG_DISPLAY_BOARDINFO 159 int checkboard(void) 160 { 161 puts("Board:\tUniversal C210\n"); 162 return 0; 163 } 164 #endif 165 166 #ifdef CONFIG_GENERIC_MMC 167 int board_mmc_init(bd_t *bis) 168 { 169 int err; 170 171 switch (get_hwrev()) { 172 case 0: 173 /* 174 * Set the low to enable LDO_EN 175 * But when you use the test board for eMMC booting 176 * you should set it HIGH since it removes the inverter 177 */ 178 /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ 179 s5p_gpio_direction_output(&gpio1->e3, 6, 0); 180 break; 181 default: 182 /* 183 * Default reset state is High and there's no inverter 184 * But set it as HIGH to ensure 185 */ 186 /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ 187 s5p_gpio_direction_output(&gpio1->e1, 3, 1); 188 break; 189 } 190 191 /* 192 * MMC device init 193 * mmc0 : eMMC (8-bit buswidth) 194 * mmc2 : SD card (4-bit buswidth) 195 */ 196 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); 197 if (err) 198 debug("SDMMC0 not configured\n"); 199 else 200 err = s5p_mmc_init(0, 8); 201 202 /* T-flash detect */ 203 s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); 204 s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); 205 206 /* 207 * Check the T-flash detect pin 208 * GPX3[4] T-flash detect pin 209 */ 210 if (!s5p_gpio_get_value(&gpio2->x3, 4)) { 211 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); 212 if (err) 213 debug("SDMMC2 not configured\n"); 214 else 215 err = s5p_mmc_init(2, 4); 216 } 217 218 return err; 219 220 } 221 #endif 222 223 #ifdef CONFIG_USB_GADGET 224 static int s5pc210_phy_control(int on) 225 { 226 int ret = 0; 227 struct pmic *p = get_pmic(); 228 229 if (pmic_probe(p)) 230 return -1; 231 232 if (on) { 233 ret |= pmic_set_output(p, 234 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, 235 MAX8998_SAFEOUT1, LDO_ON); 236 ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, 237 MAX8998_LDO3, LDO_ON); 238 ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, 239 MAX8998_LDO8, LDO_ON); 240 241 } else { 242 ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, 243 MAX8998_LDO8, LDO_OFF); 244 ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, 245 MAX8998_LDO3, LDO_OFF); 246 ret |= pmic_set_output(p, 247 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, 248 MAX8998_SAFEOUT1, LDO_OFF); 249 } 250 251 if (ret) { 252 puts("MAX8998 LDO setting error!\n"); 253 return -1; 254 } 255 256 return 0; 257 } 258 259 struct s3c_plat_otg_data s5pc210_otg_data = { 260 .phy_control = s5pc210_phy_control, 261 .regs_phy = EXYNOS4_USBPHY_BASE, 262 .regs_otg = EXYNOS4_USBOTG_BASE, 263 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 264 .usb_flags = PHY0_SLEEP, 265 }; 266 #endif 267 268 int board_early_init_f(void) 269 { 270 wdt_stop(); 271 272 return 0; 273 } 274 275 #ifdef CONFIG_SOFT_SPI 276 static void soft_spi_init(void) 277 { 278 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK, 279 CONFIG_SOFT_SPI_MODE & SPI_CPOL); 280 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1); 281 gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO); 282 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS, 283 !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); 284 } 285 286 void spi_cs_activate(struct spi_slave *slave) 287 { 288 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, 289 !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); 290 SPI_SCL(1); 291 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, 292 CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH); 293 } 294 295 void spi_cs_deactivate(struct spi_slave *slave) 296 { 297 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, 298 !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); 299 } 300 301 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 302 { 303 return bus == 0 && cs == 0; 304 } 305 306 void universal_spi_scl(int bit) 307 { 308 gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit); 309 } 310 311 void universal_spi_sda(int bit) 312 { 313 gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit); 314 } 315 316 int universal_spi_read(void) 317 { 318 return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO); 319 } 320 #endif 321 322 static void init_pmic_lcd(void) 323 { 324 unsigned char val; 325 int ret = 0; 326 327 struct pmic *p = get_pmic(); 328 329 if (pmic_probe(p)) 330 return; 331 332 /* LDO7 1.8V */ 333 val = 0x02; /* (1800 - 1600) / 100; */ 334 ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val); 335 336 /* LDO17 3.0V */ 337 val = 0xe; /* (3000 - 1600) / 100; */ 338 ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val); 339 340 /* Disable unneeded regulators */ 341 /* 342 * ONOFF1 343 * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON 344 * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON 345 */ 346 val = 0xB9; 347 ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val); 348 349 /* ONOFF2 350 * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON, 351 * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF 352 */ 353 val = 0x50; 354 ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val); 355 356 /* ONOFF3 357 * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF 358 * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF 359 */ 360 val = 0x00; 361 ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val); 362 363 if (ret) 364 puts("LCD pmic initialisation error!\n"); 365 } 366 367 static void lcd_cfg_gpio(void) 368 { 369 unsigned int i, f3_end = 4; 370 371 for (i = 0; i < 8; i++) { 372 /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ 373 s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2)); 374 s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2)); 375 s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2)); 376 /* pull-up/down disable */ 377 s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE); 378 s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE); 379 s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE); 380 381 /* drive strength to max (24bit) */ 382 s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X); 383 s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); 384 s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X); 385 s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW); 386 s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X); 387 s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); 388 } 389 390 for (i = 0; i < f3_end; i++) { 391 /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ 392 s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2)); 393 /* pull-up/down disable */ 394 s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE); 395 /* drive strength to max (24bit) */ 396 s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X); 397 s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW); 398 } 399 400 /* gpio pad configuration for LCD reset. */ 401 s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT); 402 403 spi_init(); 404 } 405 406 static void reset_lcd(void) 407 { 408 s5p_gpio_set_value(&gpio2->y4, 5, 1); 409 udelay(10000); 410 s5p_gpio_set_value(&gpio2->y4, 5, 0); 411 udelay(10000); 412 s5p_gpio_set_value(&gpio2->y4, 5, 1); 413 udelay(100); 414 } 415 416 static void lcd_power_on(void) 417 { 418 struct pmic *p = get_pmic(); 419 420 if (pmic_probe(p)) 421 return; 422 423 pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON); 424 pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON); 425 } 426 427 vidinfo_t panel_info = { 428 .vl_freq = 60, 429 .vl_col = 480, 430 .vl_row = 800, 431 .vl_width = 480, 432 .vl_height = 800, 433 .vl_clkp = CONFIG_SYS_HIGH, 434 .vl_hsp = CONFIG_SYS_HIGH, 435 .vl_vsp = CONFIG_SYS_HIGH, 436 .vl_dp = CONFIG_SYS_HIGH, 437 438 .vl_bpix = 5, /* Bits per pixel */ 439 440 /* LD9040 LCD Panel */ 441 .vl_hspw = 2, 442 .vl_hbpd = 16, 443 .vl_hfpd = 16, 444 445 .vl_vspw = 2, 446 .vl_vbpd = 8, 447 .vl_vfpd = 8, 448 .vl_cmd_allow_len = 0xf, 449 450 .win_id = 0, 451 .cfg_gpio = lcd_cfg_gpio, 452 .backlight_on = NULL, 453 .lcd_power_on = lcd_power_on, 454 .reset_lcd = reset_lcd, 455 .dual_lcd_enabled = 0, 456 457 .init_delay = 0, 458 .power_on_delay = 10000, 459 .reset_delay = 10000, 460 .interface_mode = FIMD_RGB_INTERFACE, 461 .mipi_enabled = 0, 462 }; 463 464 void init_panel_info(vidinfo_t *vid) 465 { 466 vid->logo_on = 1; 467 vid->resolution = HD_RESOLUTION; 468 vid->rgb_mode = MODE_RGB_P; 469 470 #ifdef CONFIG_TIZEN 471 get_tizen_logo_info(vid); 472 #endif 473 474 /* for LD9040. */ 475 vid->pclk_name = 1; /* MPLL */ 476 vid->sclk_div = 1; 477 478 vid->cfg_ldo = ld9040_cfg_ldo; 479 vid->enable_ldo = ld9040_enable_ldo; 480 481 setenv("lcdinfo", "lcd=ld9040"); 482 } 483 484 int board_init(void) 485 { 486 gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; 487 gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; 488 489 gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; 490 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 491 492 #if defined(CONFIG_PMIC) 493 pmic_init(); 494 init_pmic_lcd(); 495 #endif 496 #ifdef CONFIG_SOFT_SPI 497 soft_spi_init(); 498 #endif 499 check_hw_revision(); 500 printf("HW Revision:\t0x%x\n", board_rev); 501 502 return 0; 503 } 504