1 /* 2 * Copyright (C) 2010 Samsung Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/arch/adc.h> 28 #include <asm/arch/gpio.h> 29 #include <asm/arch/mmc.h> 30 #include <pmic.h> 31 #include <usb/s3c_udc.h> 32 #include <asm/arch/cpu.h> 33 #include <max8998_pmic.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 struct exynos4_gpio_part1 *gpio1; 38 struct exynos4_gpio_part2 *gpio2; 39 unsigned int board_rev; 40 41 u32 get_board_rev(void) 42 { 43 return board_rev; 44 } 45 46 static int get_hwrev(void) 47 { 48 return board_rev & 0xFF; 49 } 50 51 static void check_hw_revision(void); 52 53 int board_init(void) 54 { 55 gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; 56 gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; 57 58 gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; 59 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 60 61 check_hw_revision(); 62 printf("HW Revision:\t0x%x\n", board_rev); 63 64 #if defined(CONFIG_PMIC) 65 pmic_init(); 66 #endif 67 68 return 0; 69 } 70 71 int dram_init(void) 72 { 73 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 74 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 75 76 return 0; 77 } 78 79 void dram_init_banksize(void) 80 { 81 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 82 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 83 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 84 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 85 } 86 87 static unsigned short get_adc_value(int channel) 88 { 89 struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); 90 unsigned short ret = 0; 91 unsigned int reg; 92 unsigned int loop = 0; 93 94 writel(channel & 0xF, &adc->adcmux); 95 writel((1 << 14) | (49 << 6), &adc->adccon); 96 writel(1000 & 0xffff, &adc->adcdly); 97 writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */ 98 udelay(10); 99 writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */ 100 udelay(10); 101 102 do { 103 udelay(1); 104 reg = readl(&adc->adccon); 105 } while (!(reg & (1 << 15)) && (loop++ < 1000)); 106 107 ret = readl(&adc->adcdat0) & 0xFFF; 108 109 return ret; 110 } 111 112 static unsigned int get_hw_revision(void) 113 { 114 int hwrev, mode0, mode1; 115 116 mode0 = get_adc_value(1); /* HWREV_MODE0 */ 117 mode1 = get_adc_value(2); /* HWREV_MODE1 */ 118 119 /* 120 * XXX Always set the default hwrev as the latest board 121 * ADC = (voltage) / 3.3 * 4096 122 */ 123 hwrev = 3; 124 125 #define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max)) 126 if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200)) 127 hwrev = 0x0; /* 0.01V 0.01V */ 128 if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200)) 129 hwrev = 0x1; /* 610mV 0.01V */ 130 if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200)) 131 hwrev = 0x2; /* 1.16V 0.01V */ 132 if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200)) 133 hwrev = 0x3; /* 1.79V 0.01V */ 134 #undef IS_RANGE 135 136 debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev); 137 138 return hwrev; 139 } 140 141 static void check_hw_revision(void) 142 { 143 int hwrev; 144 145 hwrev = get_hw_revision(); 146 147 board_rev |= hwrev; 148 } 149 150 #ifdef CONFIG_DISPLAY_BOARDINFO 151 int checkboard(void) 152 { 153 puts("Board:\tUniversal C210\n"); 154 return 0; 155 } 156 #endif 157 158 #ifdef CONFIG_GENERIC_MMC 159 int board_mmc_init(bd_t *bis) 160 { 161 int i, err; 162 163 switch (get_hwrev()) { 164 case 0: 165 /* 166 * Set the low to enable LDO_EN 167 * But when you use the test board for eMMC booting 168 * you should set it HIGH since it removes the inverter 169 */ 170 /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ 171 s5p_gpio_direction_output(&gpio1->e3, 6, 0); 172 break; 173 default: 174 /* 175 * Default reset state is High and there's no inverter 176 * But set it as HIGH to ensure 177 */ 178 /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ 179 s5p_gpio_direction_output(&gpio1->e1, 3, 1); 180 break; 181 } 182 183 /* 184 * eMMC GPIO: 185 * SDR 8-bit@48MHz at MMC0 186 * GPK0[0] SD_0_CLK(2) 187 * GPK0[1] SD_0_CMD(2) 188 * GPK0[2] SD_0_CDn -> Not used 189 * GPK0[3:6] SD_0_DATA[0:3](2) 190 * GPK1[3:6] SD_0_DATA[0:3](3) 191 * 192 * DDR 4-bit@26MHz at MMC4 193 * GPK0[0] SD_4_CLK(3) 194 * GPK0[1] SD_4_CMD(3) 195 * GPK0[2] SD_4_CDn -> Not used 196 * GPK0[3:6] SD_4_DATA[0:3](3) 197 * GPK1[3:6] SD_4_DATA[4:7](4) 198 */ 199 for (i = 0; i < 7; i++) { 200 if (i == 2) 201 continue; 202 /* GPK0[0:6] special function 2 */ 203 s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2); 204 /* GPK0[0:6] pull disable */ 205 s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); 206 /* GPK0[0:6] drv 4x */ 207 s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); 208 } 209 210 for (i = 3; i < 7; i++) { 211 /* GPK1[3:6] special function 3 */ 212 s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3); 213 /* GPK1[3:6] pull disable */ 214 s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); 215 /* GPK1[3:6] drv 4x */ 216 s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); 217 } 218 219 /* T-flash detect */ 220 s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); 221 s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); 222 223 /* 224 * MMC device init 225 * mmc0 : eMMC (8-bit buswidth) 226 * mmc2 : SD card (4-bit buswidth) 227 */ 228 err = s5p_mmc_init(0, 8); 229 230 /* 231 * Check the T-flash detect pin 232 * GPX3[4] T-flash detect pin 233 */ 234 if (!s5p_gpio_get_value(&gpio2->x3, 4)) { 235 /* 236 * SD card GPIO: 237 * GPK2[0] SD_2_CLK(2) 238 * GPK2[1] SD_2_CMD(2) 239 * GPK2[2] SD_2_CDn -> Not used 240 * GPK2[3:6] SD_2_DATA[0:3](2) 241 */ 242 for (i = 0; i < 7; i++) { 243 if (i == 2) 244 continue; 245 /* GPK2[0:6] special function 2 */ 246 s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2); 247 /* GPK2[0:6] pull disable */ 248 s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); 249 /* GPK2[0:6] drv 4x */ 250 s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); 251 } 252 err = s5p_mmc_init(2, 4); 253 } 254 255 return err; 256 257 } 258 #endif 259 260 #ifdef CONFIG_USB_GADGET 261 static int s5pc210_phy_control(int on) 262 { 263 int ret = 0; 264 struct pmic *p = get_pmic(); 265 266 if (pmic_probe(p)) 267 return -1; 268 269 if (on) { 270 ret |= pmic_set_output(p, 271 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, 272 MAX8998_SAFEOUT1, LDO_ON); 273 ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, 274 MAX8998_LDO3, LDO_ON); 275 ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, 276 MAX8998_LDO8, LDO_ON); 277 278 } else { 279 ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, 280 MAX8998_LDO8, LDO_OFF); 281 ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, 282 MAX8998_LDO3, LDO_OFF); 283 ret |= pmic_set_output(p, 284 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, 285 MAX8998_SAFEOUT1, LDO_OFF); 286 } 287 288 if (ret) { 289 puts("MAX8998 LDO setting error!\n"); 290 return -1; 291 } 292 293 return 0; 294 } 295 296 struct s3c_plat_otg_data s5pc210_otg_data = { 297 .phy_control = s5pc210_phy_control, 298 .regs_phy = EXYNOS4_USBPHY_BASE, 299 .regs_otg = EXYNOS4_USBOTG_BASE, 300 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 301 .usb_flags = PHY0_SLEEP, 302 }; 303 #endif 304