1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <lcd.h> 12 #include <asm/io.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/gpio.h> 15 #include <asm/arch/mmc.h> 16 #include <asm/arch/pinmux.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/clk.h> 19 #include <asm/arch/mipi_dsim.h> 20 #include <asm/arch/watchdog.h> 21 #include <asm/arch/power.h> 22 #include <power/pmic.h> 23 #include <usb/s3c_udc.h> 24 #include <power/max8997_pmic.h> 25 #include <libtizen.h> 26 #include <power/max8997_muic.h> 27 #include <power/battery.h> 28 #include <power/max17042_fg.h> 29 #include <usb.h> 30 #include <usb_mass_storage.h> 31 32 #include "setup.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 unsigned int board_rev; 37 38 #ifdef CONFIG_REVISION_TAG 39 u32 get_board_rev(void) 40 { 41 return board_rev; 42 } 43 #endif 44 45 static void check_hw_revision(void); 46 struct s3c_plat_otg_data s5pc210_otg_data; 47 48 int board_init(void) 49 { 50 gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR; 51 52 check_hw_revision(); 53 printf("HW Revision:\t0x%x\n", board_rev); 54 55 return 0; 56 } 57 58 void i2c_init_board(void) 59 { 60 struct exynos4_gpio_part1 *gpio1 = 61 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 62 struct exynos4_gpio_part2 *gpio2 = 63 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 64 65 /* I2C_5 -> PMIC -> Adapter 0 */ 66 s5p_gpio_direction_output(&gpio1->b, 7, 1); 67 s5p_gpio_direction_output(&gpio1->b, 6, 1); 68 /* I2C_9 -> FG -> Adapter 1 */ 69 s5p_gpio_direction_output(&gpio2->y4, 0, 1); 70 s5p_gpio_direction_output(&gpio2->y4, 1, 1); 71 } 72 73 static void trats_low_power_mode(void) 74 { 75 struct exynos4_clock *clk = 76 (struct exynos4_clock *)samsung_get_base_clock(); 77 struct exynos4_power *pwr = 78 (struct exynos4_power *)samsung_get_base_power(); 79 80 /* Power down CORE1 */ 81 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ 82 writel(0x0, &pwr->arm_core1_configuration); 83 84 /* Change the APLL frequency */ 85 /* ENABLE (1 enable) | LOCKED (1 locked) */ 86 /* [31] | [29] */ 87 /* FSEL | MDIV | PDIV | SDIV */ 88 /* [27] | [25:16] | [13:8] | [2:0] */ 89 writel(0xa0c80604, &clk->apll_con0); 90 91 /* Change CPU0 clock divider */ 92 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ 93 /* [30:28] | [26:24] | [22:20] | [18:16] */ 94 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ 95 /* [14:12] | [10:8] | [6:4] | [2:0] */ 96 writel(0x00000100, &clk->div_cpu0); 97 98 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ 99 while (readl(&clk->div_stat_cpu0) & 0x1111111) 100 continue; 101 102 /* Change clock divider ratio for DMC */ 103 /* DMCP_RATIO | DMCD_RATIO */ 104 /* [22:20] | [18:16] */ 105 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ 106 /* [14:12] | [10:8] | [6:4] | [2:0] */ 107 writel(0x13113117, &clk->div_dmc0); 108 109 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ 110 while (readl(&clk->div_stat_dmc0) & 0x11111111) 111 continue; 112 113 /* Turn off unnecessary power domains */ 114 writel(0x0, &pwr->xxti_configuration); /* XXTI */ 115 writel(0x0, &pwr->cam_configuration); /* CAM */ 116 writel(0x0, &pwr->tv_configuration); /* TV */ 117 writel(0x0, &pwr->mfc_configuration); /* MFC */ 118 writel(0x0, &pwr->g3d_configuration); /* G3D */ 119 writel(0x0, &pwr->gps_configuration); /* GPS */ 120 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ 121 122 /* Turn off unnecessary clocks */ 123 writel(0x0, &clk->gate_ip_cam); /* CAM */ 124 writel(0x0, &clk->gate_ip_tv); /* TV */ 125 writel(0x0, &clk->gate_ip_mfc); /* MFC */ 126 writel(0x0, &clk->gate_ip_g3d); /* G3D */ 127 writel(0x0, &clk->gate_ip_image); /* IMAGE */ 128 writel(0x0, &clk->gate_ip_gps); /* GPS */ 129 } 130 131 static int pmic_init_max8997(void) 132 { 133 struct pmic *p = pmic_get("MAX8997_PMIC"); 134 int i = 0, ret = 0; 135 u32 val; 136 137 if (pmic_probe(p)) 138 return -1; 139 140 /* BUCK1 VARM: 1.2V */ 141 val = (1200000 - 650000) / 25000; 142 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val); 143 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 144 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val); 145 146 /* BUCK2 VINT: 1.1V */ 147 val = (1100000 - 650000) / 25000; 148 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val); 149 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 150 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val); 151 152 153 /* BUCK3 G3D: 1.1V - OFF */ 154 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val); 155 val &= ~ENBUCK; 156 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val); 157 158 val = (1100000 - 750000) / 50000; 159 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val); 160 161 /* BUCK4 CAMISP: 1.2V - OFF */ 162 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val); 163 val &= ~ENBUCK; 164 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val); 165 166 val = (1200000 - 650000) / 25000; 167 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val); 168 169 /* BUCK5 VMEM: 1.2V */ 170 val = (1200000 - 650000) / 25000; 171 for (i = 0; i < 8; i++) 172 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val); 173 174 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 175 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val); 176 177 /* BUCK6 CAM AF: 2.8V */ 178 /* No Voltage Setting Register */ 179 /* GNSLCT 3.0X */ 180 val = GNSLCT; 181 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val); 182 183 /* BUCK7 VCC_SUB: 2.0V */ 184 val = (2000000 - 750000) / 50000; 185 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val); 186 187 /* LDO1 VADC: 3.3V */ 188 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 189 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val); 190 191 /* LDO1 Disable active discharging */ 192 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val); 193 val &= ~LDO_ADE; 194 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val); 195 196 /* LDO2 VALIVE: 1.1V */ 197 val = max8997_reg_ldo(1100000) | EN_LDO; 198 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val); 199 200 /* LDO3 VUSB/MIPI: 1.1V */ 201 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */ 202 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val); 203 204 /* LDO4 VMIPI: 1.8V */ 205 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 206 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val); 207 208 /* LDO5 VHSIC: 1.2V */ 209 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */ 210 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val); 211 212 /* LDO6 VCC_1.8V_PDA: 1.8V */ 213 val = max8997_reg_ldo(1800000) | EN_LDO; 214 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val); 215 216 /* LDO7 CAM_ISP: 1.8V */ 217 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 218 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val); 219 220 /* LDO8 VDAC/VUSB: 3.3V */ 221 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 222 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val); 223 224 /* LDO9 VCC_2.8V_PDA: 2.8V */ 225 val = max8997_reg_ldo(2800000) | EN_LDO; 226 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val); 227 228 /* LDO10 VPLL: 1.1V */ 229 val = max8997_reg_ldo(1100000) | EN_LDO; 230 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val); 231 232 /* LDO11 TOUCH: 2.8V */ 233 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 234 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val); 235 236 /* LDO12 VTCAM: 1.8V */ 237 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 238 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val); 239 240 /* LDO13 VCC_3.0_LCD: 3.0V */ 241 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 242 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val); 243 244 /* LDO14 MOTOR: 3.0V */ 245 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 246 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val); 247 248 /* LDO15 LED_A: 2.8V */ 249 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 250 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val); 251 252 /* LDO16 CAM_SENSOR: 1.8V */ 253 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 254 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val); 255 256 /* LDO17 VTF: 2.8V */ 257 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 258 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val); 259 260 /* LDO18 TOUCH_LED 3.3V */ 261 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 262 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val); 263 264 /* LDO21 VDDQ: 1.2V */ 265 val = max8997_reg_ldo(1200000) | EN_LDO; 266 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val); 267 268 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */ 269 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) | 270 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2; 271 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val); 272 273 if (ret) { 274 puts("MAX8997 PMIC setting error!\n"); 275 return -1; 276 } 277 return 0; 278 } 279 280 int power_init_board(void) 281 { 282 int chrg, ret; 283 struct power_battery *pb; 284 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; 285 286 /* 287 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected 288 * to logical I2C adapter 0 289 * 290 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected 291 * to logical I2C adapter 1 292 */ 293 ret = pmic_init(I2C_0); 294 ret |= pmic_init_max8997(); 295 ret |= power_fg_init(I2C_1); 296 ret |= power_muic_init(I2C_0); 297 ret |= power_bat_init(0); 298 if (ret) 299 return ret; 300 301 p_fg = pmic_get("MAX17042_FG"); 302 if (!p_fg) { 303 puts("MAX17042_FG: Not found\n"); 304 return -ENODEV; 305 } 306 307 p_chrg = pmic_get("MAX8997_PMIC"); 308 if (!p_chrg) { 309 puts("MAX8997_PMIC: Not found\n"); 310 return -ENODEV; 311 } 312 313 p_muic = pmic_get("MAX8997_MUIC"); 314 if (!p_muic) { 315 puts("MAX8997_MUIC: Not found\n"); 316 return -ENODEV; 317 } 318 319 p_bat = pmic_get("BAT_TRATS"); 320 if (!p_bat) { 321 puts("BAT_TRATS: Not found\n"); 322 return -ENODEV; 323 } 324 325 p_fg->parent = p_bat; 326 p_chrg->parent = p_bat; 327 p_muic->parent = p_bat; 328 329 p_bat->low_power_mode = trats_low_power_mode; 330 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); 331 332 pb = p_bat->pbat; 333 chrg = p_muic->chrg->chrg_type(p_muic); 334 debug("CHARGER TYPE: %d\n", chrg); 335 336 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { 337 puts("No battery detected\n"); 338 return -1; 339 } 340 341 p_fg->fg->fg_battery_check(p_fg, p_bat); 342 343 if (pb->bat->state == CHARGE && chrg == CHARGER_USB) 344 puts("CHARGE Battery !\n"); 345 346 return 0; 347 } 348 349 int dram_init(void) 350 { 351 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 352 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + 353 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + 354 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); 355 356 return 0; 357 } 358 359 void dram_init_banksize(void) 360 { 361 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 362 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 363 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 364 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 365 gd->bd->bi_dram[2].start = PHYS_SDRAM_3; 366 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; 367 gd->bd->bi_dram[3].start = PHYS_SDRAM_4; 368 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; 369 } 370 371 static unsigned int get_hw_revision(void) 372 { 373 struct exynos4_gpio_part1 *gpio = 374 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 375 int hwrev = 0; 376 int i; 377 378 /* hw_rev[3:0] == GPE1[3:0] */ 379 for (i = 0; i < 4; i++) { 380 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); 381 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); 382 } 383 384 udelay(1); 385 386 for (i = 0; i < 4; i++) 387 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); 388 389 debug("hwrev 0x%x\n", hwrev); 390 391 return hwrev; 392 } 393 394 static void check_hw_revision(void) 395 { 396 int hwrev; 397 398 hwrev = get_hw_revision(); 399 400 board_rev |= hwrev; 401 } 402 403 #ifdef CONFIG_DISPLAY_BOARDINFO 404 int checkboard(void) 405 { 406 puts("Board:\tTRATS\n"); 407 return 0; 408 } 409 #endif 410 411 #ifdef CONFIG_GENERIC_MMC 412 int board_mmc_init(bd_t *bis) 413 { 414 struct exynos4_gpio_part2 *gpio = 415 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 416 int err; 417 418 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 419 s5p_gpio_direction_output(&gpio->k0, 2, 1); 420 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); 421 422 /* 423 * MMC device init 424 * mmc0 : eMMC (8-bit buswidth) 425 * mmc2 : SD card (4-bit buswidth) 426 */ 427 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); 428 if (err) 429 debug("SDMMC0 not configured\n"); 430 else 431 err = s5p_mmc_init(0, 8); 432 433 /* T-flash detect */ 434 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); 435 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); 436 437 /* 438 * Check the T-flash detect pin 439 * GPX3[4] T-flash detect pin 440 */ 441 if (!s5p_gpio_get_value(&gpio->x3, 4)) { 442 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); 443 if (err) 444 debug("SDMMC2 not configured\n"); 445 else 446 err = s5p_mmc_init(2, 4); 447 } 448 449 return err; 450 } 451 #endif 452 453 #ifdef CONFIG_USB_GADGET 454 static int s5pc210_phy_control(int on) 455 { 456 int ret = 0; 457 u32 val = 0; 458 struct pmic *p = pmic_get("MAX8997_PMIC"); 459 if (!p) 460 return -ENODEV; 461 462 if (pmic_probe(p)) 463 return -1; 464 465 if (on) { 466 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 467 ENSAFEOUT1, LDO_ON); 468 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 469 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); 470 471 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 472 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); 473 } else { 474 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 475 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); 476 477 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 478 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); 479 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 480 ENSAFEOUT1, LDO_OFF); 481 } 482 483 if (ret) { 484 puts("MAX8997 LDO setting error!\n"); 485 return -1; 486 } 487 488 return 0; 489 } 490 491 struct s3c_plat_otg_data s5pc210_otg_data = { 492 .phy_control = s5pc210_phy_control, 493 .regs_phy = EXYNOS4_USBPHY_BASE, 494 .regs_otg = EXYNOS4_USBOTG_BASE, 495 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 496 .usb_flags = PHY0_SLEEP, 497 }; 498 499 int board_usb_init(int index, enum usb_init_type init) 500 { 501 debug("USB_udc_probe\n"); 502 return s3c_udc_probe(&s5pc210_otg_data); 503 } 504 #endif 505 506 static void pmic_reset(void) 507 { 508 struct exynos4_gpio_part2 *gpio = 509 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 510 511 s5p_gpio_direction_output(&gpio->x0, 7, 1); 512 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); 513 } 514 515 static void board_clock_init(void) 516 { 517 struct exynos4_clock *clk = 518 (struct exynos4_clock *)samsung_get_base_clock(); 519 520 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 521 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 522 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 523 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 524 525 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 526 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 527 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 528 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 529 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 530 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 531 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 532 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 533 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 534 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 535 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 536 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 537 538 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 539 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 540 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 541 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 542 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 543 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 544 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 545 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 546 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 547 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 548 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 549 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 550 551 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 552 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 553 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 554 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 555 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 556 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 557 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 558 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 559 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 560 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 561 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 562 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 563 } 564 565 static void board_power_init(void) 566 { 567 struct exynos4_power *pwr = 568 (struct exynos4_power *)samsung_get_base_power(); 569 570 /* PS HOLD */ 571 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 572 573 /* Set power down */ 574 writel(0, (unsigned int)&pwr->cam_configuration); 575 writel(0, (unsigned int)&pwr->tv_configuration); 576 writel(0, (unsigned int)&pwr->mfc_configuration); 577 writel(0, (unsigned int)&pwr->g3d_configuration); 578 writel(0, (unsigned int)&pwr->lcd1_configuration); 579 writel(0, (unsigned int)&pwr->gps_configuration); 580 writel(0, (unsigned int)&pwr->gps_alive_configuration); 581 582 /* It is necessary to power down core 1 */ 583 /* to successfully boot CPU1 in kernel */ 584 writel(0, (unsigned int)&pwr->arm_core1_configuration); 585 } 586 587 static void board_uart_init(void) 588 { 589 struct exynos4_gpio_part1 *gpio1 = 590 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 591 struct exynos4_gpio_part2 *gpio2 = 592 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 593 int i; 594 595 /* 596 * UART2 GPIOs 597 * GPA1CON[0] = UART_2_RXD(2) 598 * GPA1CON[1] = UART_2_TXD(2) 599 * GPA1CON[2] = I2C_3_SDA (3) 600 * GPA1CON[3] = I2C_3_SCL (3) 601 */ 602 603 for (i = 0; i < 4; i++) { 604 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); 605 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); 606 } 607 608 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 609 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); 610 s5p_gpio_direction_output(&gpio2->y4, 7, 1); 611 } 612 613 int board_early_init_f(void) 614 { 615 wdt_stop(); 616 pmic_reset(); 617 board_clock_init(); 618 board_uart_init(); 619 board_power_init(); 620 621 return 0; 622 } 623 624 void exynos_reset_lcd(void) 625 { 626 struct exynos4_gpio_part2 *gpio2 = 627 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 628 629 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 630 udelay(10000); 631 s5p_gpio_direction_output(&gpio2->y4, 5, 0); 632 udelay(10000); 633 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 634 } 635 636 static int lcd_power(void) 637 { 638 int ret = 0; 639 struct pmic *p = pmic_get("MAX8997_PMIC"); 640 if (!p) 641 return -ENODEV; 642 643 if (pmic_probe(p)) 644 return 0; 645 646 /* LDO15 voltage: 2.2v */ 647 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 648 /* LDO13 voltage: 3.0v */ 649 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 650 651 if (ret) { 652 puts("MAX8997 LDO setting error!\n"); 653 return -1; 654 } 655 656 return 0; 657 } 658 659 static struct mipi_dsim_config dsim_config = { 660 .e_interface = DSIM_VIDEO, 661 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 662 .e_pixel_format = DSIM_24BPP_888, 663 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 664 .e_no_data_lane = DSIM_DATA_LANE_4, 665 .e_byte_clk = DSIM_PLL_OUT_DIV8, 666 .hfp = 1, 667 668 .p = 3, 669 .m = 120, 670 .s = 1, 671 672 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 673 .pll_stable_time = 500, 674 675 /* escape clk : 10MHz */ 676 .esc_clk = 20 * 1000000, 677 678 /* stop state holding counter after bta change count 0 ~ 0xfff */ 679 .stop_holding_cnt = 0x7ff, 680 /* bta timeout 0 ~ 0xff */ 681 .bta_timeout = 0xff, 682 /* lp rx timeout 0 ~ 0xffff */ 683 .rx_timeout = 0xffff, 684 }; 685 686 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { 687 .lcd_panel_info = NULL, 688 .dsim_config = &dsim_config, 689 }; 690 691 static struct mipi_dsim_lcd_device mipi_lcd_device = { 692 .name = "s6e8ax0", 693 .id = -1, 694 .bus_id = 0, 695 .platform_data = (void *)&s6e8ax0_platform_data, 696 }; 697 698 static int mipi_power(void) 699 { 700 int ret = 0; 701 struct pmic *p = pmic_get("MAX8997_PMIC"); 702 if (!p) 703 return -ENODEV; 704 705 if (pmic_probe(p)) 706 return 0; 707 708 /* LDO3 voltage: 1.1v */ 709 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 710 /* LDO4 voltage: 1.8v */ 711 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 712 713 if (ret) { 714 puts("MAX8997 LDO setting error!\n"); 715 return -1; 716 } 717 718 return 0; 719 } 720 721 vidinfo_t panel_info = { 722 .vl_freq = 60, 723 .vl_col = 720, 724 .vl_row = 1280, 725 .vl_width = 720, 726 .vl_height = 1280, 727 .vl_clkp = CONFIG_SYS_HIGH, 728 .vl_hsp = CONFIG_SYS_LOW, 729 .vl_vsp = CONFIG_SYS_LOW, 730 .vl_dp = CONFIG_SYS_LOW, 731 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ 732 733 /* s6e8ax0 Panel infomation */ 734 .vl_hspw = 5, 735 .vl_hbpd = 10, 736 .vl_hfpd = 10, 737 738 .vl_vspw = 2, 739 .vl_vbpd = 1, 740 .vl_vfpd = 13, 741 .vl_cmd_allow_len = 0xf, 742 743 .win_id = 3, 744 .dual_lcd_enabled = 0, 745 746 .init_delay = 0, 747 .power_on_delay = 0, 748 .reset_delay = 0, 749 .interface_mode = FIMD_RGB_INTERFACE, 750 .mipi_enabled = 1, 751 }; 752 753 void init_panel_info(vidinfo_t *vid) 754 { 755 vid->logo_on = 1, 756 vid->resolution = HD_RESOLUTION, 757 vid->rgb_mode = MODE_RGB_P, 758 759 #ifdef CONFIG_TIZEN 760 get_tizen_logo_info(vid); 761 #endif 762 mipi_lcd_device.reverse_panel = 1; 763 764 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); 765 s6e8ax0_platform_data.lcd_power = lcd_power; 766 s6e8ax0_platform_data.mipi_power = mipi_power; 767 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; 768 s6e8ax0_platform_data.lcd_panel_info = (void *)vid; 769 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 770 s6e8ax0_init(); 771 exynos_set_dsim_platform_data(&s6e8ax0_platform_data); 772 773 setenv("lcdinfo", "lcd=s6e8ax0"); 774 } 775