1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <lcd.h> 28 #include <asm/io.h> 29 #include <asm/arch/cpu.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/mmc.h> 32 #include <asm/arch/clock.h> 33 #include <asm/arch/clk.h> 34 #include <asm/arch/mipi_dsim.h> 35 #include <asm/arch/watchdog.h> 36 #include <asm/arch/power.h> 37 #include <pmic.h> 38 #include <usb/s3c_udc.h> 39 #include <max8997_pmic.h> 40 #include <libtizen.h> 41 42 #include "setup.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 unsigned int board_rev; 47 48 #ifdef CONFIG_REVISION_TAG 49 u32 get_board_rev(void) 50 { 51 return board_rev; 52 } 53 #endif 54 55 static void check_hw_revision(void); 56 57 static int hwrevision(int rev) 58 { 59 return (board_rev & 0xf) == rev; 60 } 61 62 struct s3c_plat_otg_data s5pc210_otg_data; 63 64 int board_init(void) 65 { 66 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 67 68 check_hw_revision(); 69 printf("HW Revision:\t0x%x\n", board_rev); 70 71 #if defined(CONFIG_PMIC) 72 pmic_init(); 73 #endif 74 75 return 0; 76 } 77 78 void i2c_init_board(void) 79 { 80 struct exynos4_gpio_part1 *gpio1 = 81 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 82 struct exynos4_gpio_part2 *gpio2 = 83 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 84 85 /* I2C_5 -> PMIC */ 86 s5p_gpio_direction_output(&gpio1->b, 7, 1); 87 s5p_gpio_direction_output(&gpio1->b, 6, 1); 88 /* I2C_9 -> FG */ 89 s5p_gpio_direction_output(&gpio2->y4, 0, 1); 90 s5p_gpio_direction_output(&gpio2->y4, 1, 1); 91 } 92 93 int dram_init(void) 94 { 95 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 96 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 97 98 return 0; 99 } 100 101 void dram_init_banksize(void) 102 { 103 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 104 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 105 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 106 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 107 } 108 109 static unsigned int get_hw_revision(void) 110 { 111 struct exynos4_gpio_part1 *gpio = 112 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 113 int hwrev = 0; 114 int i; 115 116 /* hw_rev[3:0] == GPE1[3:0] */ 117 for (i = 0; i < 4; i++) { 118 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); 119 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); 120 } 121 122 udelay(1); 123 124 for (i = 0; i < 4; i++) 125 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); 126 127 debug("hwrev 0x%x\n", hwrev); 128 129 return hwrev; 130 } 131 132 static void check_hw_revision(void) 133 { 134 int hwrev; 135 136 hwrev = get_hw_revision(); 137 138 board_rev |= hwrev; 139 } 140 141 #ifdef CONFIG_DISPLAY_BOARDINFO 142 int checkboard(void) 143 { 144 puts("Board:\tTRATS\n"); 145 return 0; 146 } 147 #endif 148 149 #ifdef CONFIG_GENERIC_MMC 150 int board_mmc_init(bd_t *bis) 151 { 152 struct exynos4_gpio_part2 *gpio = 153 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 154 int i, err; 155 156 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 157 s5p_gpio_direction_output(&gpio->k0, 2, 1); 158 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); 159 160 /* 161 * eMMC GPIO: 162 * SDR 8-bit@48MHz at MMC0 163 * GPK0[0] SD_0_CLK(2) 164 * GPK0[1] SD_0_CMD(2) 165 * GPK0[2] SD_0_CDn -> Not used 166 * GPK0[3:6] SD_0_DATA[0:3](2) 167 * GPK1[3:6] SD_0_DATA[0:3](3) 168 * 169 * DDR 4-bit@26MHz at MMC4 170 * GPK0[0] SD_4_CLK(3) 171 * GPK0[1] SD_4_CMD(3) 172 * GPK0[2] SD_4_CDn -> Not used 173 * GPK0[3:6] SD_4_DATA[0:3](3) 174 * GPK1[3:6] SD_4_DATA[4:7](4) 175 */ 176 for (i = 0; i < 7; i++) { 177 if (i == 2) 178 continue; 179 /* GPK0[0:6] special function 2 */ 180 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2); 181 /* GPK0[0:6] pull disable */ 182 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE); 183 /* GPK0[0:6] drv 4x */ 184 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X); 185 } 186 187 for (i = 3; i < 7; i++) { 188 /* GPK1[3:6] special function 3 */ 189 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3); 190 /* GPK1[3:6] pull disable */ 191 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE); 192 /* GPK1[3:6] drv 4x */ 193 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X); 194 } 195 196 /* 197 * MMC device init 198 * mmc0 : eMMC (8-bit buswidth) 199 * mmc2 : SD card (4-bit buswidth) 200 */ 201 err = s5p_mmc_init(0, 8); 202 203 /* T-flash detect */ 204 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); 205 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); 206 207 /* 208 * Check the T-flash detect pin 209 * GPX3[4] T-flash detect pin 210 */ 211 if (!s5p_gpio_get_value(&gpio->x3, 4)) { 212 /* 213 * SD card GPIO: 214 * GPK2[0] SD_2_CLK(2) 215 * GPK2[1] SD_2_CMD(2) 216 * GPK2[2] SD_2_CDn -> Not used 217 * GPK2[3:6] SD_2_DATA[0:3](2) 218 */ 219 for (i = 0; i < 7; i++) { 220 if (i == 2) 221 continue; 222 /* GPK2[0:6] special function 2 */ 223 s5p_gpio_cfg_pin(&gpio->k2, i, 0x2); 224 /* GPK2[0:6] pull disable */ 225 s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE); 226 /* GPK2[0:6] drv 4x */ 227 s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X); 228 } 229 err = s5p_mmc_init(2, 4); 230 } 231 232 return err; 233 } 234 #endif 235 236 #ifdef CONFIG_USB_GADGET 237 static int s5pc210_phy_control(int on) 238 { 239 int ret = 0; 240 u32 val = 0; 241 struct pmic *p = get_pmic(); 242 243 if (pmic_probe(p)) 244 return -1; 245 246 if (on) { 247 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 248 ENSAFEOUT1, LDO_ON); 249 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 250 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); 251 252 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 253 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); 254 } else { 255 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 256 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); 257 258 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 259 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); 260 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 261 ENSAFEOUT1, LDO_OFF); 262 } 263 264 if (ret) { 265 puts("MAX8997 LDO setting error!\n"); 266 return -1; 267 } 268 269 return 0; 270 } 271 272 struct s3c_plat_otg_data s5pc210_otg_data = { 273 .phy_control = s5pc210_phy_control, 274 .regs_phy = EXYNOS4_USBPHY_BASE, 275 .regs_otg = EXYNOS4_USBOTG_BASE, 276 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 277 .usb_flags = PHY0_SLEEP, 278 }; 279 280 void board_usb_init(void) 281 { 282 debug("USB_udc_probe\n"); 283 s3c_udc_probe(&s5pc210_otg_data); 284 } 285 #endif 286 287 static void pmic_reset(void) 288 { 289 struct exynos4_gpio_part2 *gpio = 290 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 291 292 s5p_gpio_direction_output(&gpio->x0, 7, 1); 293 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); 294 } 295 296 static void board_clock_init(void) 297 { 298 struct exynos4_clock *clk = 299 (struct exynos4_clock *)samsung_get_base_clock(); 300 301 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 302 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 303 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 304 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 305 306 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 307 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 308 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 309 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 310 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 311 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 312 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 313 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 314 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 315 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 316 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 317 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 318 319 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 320 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 321 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 322 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 323 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 324 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 325 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 326 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 327 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 328 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 329 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 330 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 331 332 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 333 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 334 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 335 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 336 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 337 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 338 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 339 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 340 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 341 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 342 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 343 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 344 } 345 346 static void board_power_init(void) 347 { 348 struct exynos4_power *pwr = 349 (struct exynos4_power *)samsung_get_base_power(); 350 351 /* PS HOLD */ 352 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 353 354 /* Set power down */ 355 writel(0, (unsigned int)&pwr->cam_configuration); 356 writel(0, (unsigned int)&pwr->tv_configuration); 357 writel(0, (unsigned int)&pwr->mfc_configuration); 358 writel(0, (unsigned int)&pwr->g3d_configuration); 359 writel(0, (unsigned int)&pwr->lcd1_configuration); 360 writel(0, (unsigned int)&pwr->gps_configuration); 361 writel(0, (unsigned int)&pwr->gps_alive_configuration); 362 } 363 364 static void board_uart_init(void) 365 { 366 struct exynos4_gpio_part1 *gpio1 = 367 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 368 struct exynos4_gpio_part2 *gpio2 = 369 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 370 int i; 371 372 /* 373 * UART2 GPIOs 374 * GPA1CON[0] = UART_2_RXD(2) 375 * GPA1CON[1] = UART_2_TXD(2) 376 * GPA1CON[2] = I2C_3_SDA (3) 377 * GPA1CON[3] = I2C_3_SCL (3) 378 */ 379 380 for (i = 0; i < 4; i++) { 381 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); 382 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); 383 } 384 385 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 386 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); 387 s5p_gpio_direction_output(&gpio2->y4, 7, 1); 388 } 389 390 int board_early_init_f(void) 391 { 392 wdt_stop(); 393 pmic_reset(); 394 board_clock_init(); 395 board_uart_init(); 396 board_power_init(); 397 398 return 0; 399 } 400 401 static void lcd_reset(void) 402 { 403 struct exynos4_gpio_part2 *gpio2 = 404 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 405 406 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 407 udelay(10000); 408 s5p_gpio_direction_output(&gpio2->y4, 5, 0); 409 udelay(10000); 410 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 411 } 412 413 static int lcd_power(void) 414 { 415 int ret = 0; 416 struct pmic *p = get_pmic(); 417 418 if (pmic_probe(p)) 419 return 0; 420 421 /* LDO15 voltage: 2.2v */ 422 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 423 /* LDO13 voltage: 3.0v */ 424 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 425 426 if (ret) { 427 puts("MAX8997 LDO setting error!\n"); 428 return -1; 429 } 430 431 return 0; 432 } 433 434 static struct mipi_dsim_config dsim_config = { 435 .e_interface = DSIM_VIDEO, 436 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 437 .e_pixel_format = DSIM_24BPP_888, 438 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 439 .e_no_data_lane = DSIM_DATA_LANE_4, 440 .e_byte_clk = DSIM_PLL_OUT_DIV8, 441 .hfp = 1, 442 443 .p = 3, 444 .m = 120, 445 .s = 1, 446 447 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 448 .pll_stable_time = 500, 449 450 /* escape clk : 10MHz */ 451 .esc_clk = 20 * 1000000, 452 453 /* stop state holding counter after bta change count 0 ~ 0xfff */ 454 .stop_holding_cnt = 0x7ff, 455 /* bta timeout 0 ~ 0xff */ 456 .bta_timeout = 0xff, 457 /* lp rx timeout 0 ~ 0xffff */ 458 .rx_timeout = 0xffff, 459 }; 460 461 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { 462 .lcd_panel_info = NULL, 463 .dsim_config = &dsim_config, 464 }; 465 466 static struct mipi_dsim_lcd_device mipi_lcd_device = { 467 .name = "s6e8ax0", 468 .id = -1, 469 .bus_id = 0, 470 .platform_data = (void *)&s6e8ax0_platform_data, 471 }; 472 473 static int mipi_power(void) 474 { 475 int ret = 0; 476 struct pmic *p = get_pmic(); 477 478 if (pmic_probe(p)) 479 return 0; 480 481 /* LDO3 voltage: 1.1v */ 482 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 483 /* LDO4 voltage: 1.8v */ 484 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 485 486 if (ret) { 487 puts("MAX8997 LDO setting error!\n"); 488 return -1; 489 } 490 491 return 0; 492 } 493 494 vidinfo_t panel_info = { 495 .vl_freq = 60, 496 .vl_col = 720, 497 .vl_row = 1280, 498 .vl_width = 720, 499 .vl_height = 1280, 500 .vl_clkp = CONFIG_SYS_HIGH, 501 .vl_hsp = CONFIG_SYS_LOW, 502 .vl_vsp = CONFIG_SYS_LOW, 503 .vl_dp = CONFIG_SYS_LOW, 504 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ 505 506 /* s6e8ax0 Panel infomation */ 507 .vl_hspw = 5, 508 .vl_hbpd = 10, 509 .vl_hfpd = 10, 510 511 .vl_vspw = 2, 512 .vl_vbpd = 1, 513 .vl_vfpd = 13, 514 .vl_cmd_allow_len = 0xf, 515 516 .win_id = 3, 517 .cfg_gpio = NULL, 518 .backlight_on = NULL, 519 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ 520 .reset_lcd = lcd_reset, 521 .dual_lcd_enabled = 0, 522 523 .init_delay = 0, 524 .power_on_delay = 0, 525 .reset_delay = 0, 526 .interface_mode = FIMD_RGB_INTERFACE, 527 .mipi_enabled = 1, 528 }; 529 530 void init_panel_info(vidinfo_t *vid) 531 { 532 vid->logo_on = 1, 533 vid->resolution = HD_RESOLUTION, 534 vid->rgb_mode = MODE_RGB_P, 535 536 #ifdef CONFIG_TIZEN 537 get_tizen_logo_info(vid); 538 #endif 539 540 if (hwrevision(2)) 541 mipi_lcd_device.reverse_panel = 1; 542 543 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); 544 s6e8ax0_platform_data.lcd_power = lcd_power; 545 s6e8ax0_platform_data.mipi_power = mipi_power; 546 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; 547 s6e8ax0_platform_data.lcd_panel_info = (void *)vid; 548 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 549 s6e8ax0_init(); 550 exynos_set_dsim_platform_data(&s6e8ax0_platform_data); 551 552 setenv("lcdinfo", "lcd=s6e8ax0"); 553 } 554